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ds07-16201-2e fujitsu semiconductor data sheet 32-bit risc microcontroller cmos fr20 MB91103 series MB91103 n description the MB91103 is a standard single-chip microcontroller constructed around the 32-bit risc cpu (fr20 series) core with abundant i/o resources and bus control functions optimized for high-performance/high-speed cpu processing for embedded controller applications. to support the vast memory space accessed by the 32-bit cpu, the MB91103 normally operates in the external bus access mode and executes instructions on the internal 1 kb cache memory for enhanced performance. the MB91103 is optimized for applications requiring high-performance cpu processing such as navigation systems, high-performance faxs and printer controllers. n features fr20cpu 32-bit risc, load/store architecture, 5-stage pipeline operating clock frequency: 25 mhz general purpose registers: 32-bit 16 16-bit ?ed length instructions (basic instructions), 1 instruction/1 cycle memory to memory transfer, bit processing, barrel shifter processing: optimized for embedded applications function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages register interlock functions, ef?ient assembly language coding branch instructions with delay slots: reduced overhead time in branch executions internal multiplier/supported at instruction level signed 32-bit multiplication: 5 cycles signed 16-bit multiplication: 3 cycles interrupt (push pc and ps): 6 cycles, 16 priority levels (continued) n package 160-pin plastic qfp (fpt-160p-m03)
MB91103 series 2 (continued) bus interface 24-bit address bus (16 mb memory space) 32-bit/16-bit/8-bit data bus basic external bus cycle: 2 clock cycles chip select outputs for setting down to a minimum memory block size of 64 k bytes: 6 interface supported for various memory technologies time sharing input/output of data/address (area 1) dram interface (area 4 and 5) automatic wait cycle insertion: flexible setting, from 0 to 7 for each area parity check function: generates parity error interrupt unused data/address pins can be con?ured us input/output ports little endian mode supported (select 1 area from area 1 to 5) dram interface 2 banks independent control (area 4 and 5) normal mode/high speed page mode basic bus cycle: normally 5 cycles, single-cycle access possible in high speed page mode programmable waveform: automatic 1-cycle wait insertion to ras and cas cycles dram refresh cbr refresh (interval time con?urable by 6-bit timer) self-refresh mode supports 8-bit/9-bit/10-bit/12-bit column address width 2cas/1we, 2we/1cas selective cache memory 1 kb instruction cache memory 2 way set associative 32 blocks/way, 4 entries (4 words)/block dmac (dma controller) 5 channels external to external 2.5 access cycle/transfer (when 2 clock cycles = 1 access cycle) internal to external 1.5 access cycle/transfer (when 2 clock cycles = 1 access cycle) address registers (inc, dec and reload executable), 32-bit 2, 16-bit 6 transfer count register ( reload executable), 16-bit 2, 8-bit 3 transfer incident/external pins/internal resource interrupt requests/software interrupts transfer sequence: step transfer/block transfer/burst transfer/continuous transfer/cycle steal transfer (for ch. 0 and ch.1 only) transfer data length: 8-bit/6-bit/32-bit selective command chain operation possible nmi/interrupt request enables temporary stop operation uart 2 independent channels full-duplex double buffer data length: 7-bit to 9-bit (non-parity), 6-bit to 8-bit (parity) asynchronous (start-stop system), clk-synchronized communication selective multi-processor mode internal 16-bit timer operating as a proprietary baud rate generator: generates any given baud rate use external clock can be used as a transfer clock error detection: parity, frame, overrun
3 MB91103 series (continued) extended i/o serial interface inputs/outputs 8-bit data in serial format lsb ?st/msb ?st selective shift clock internal generation/external input selective a/d converter (successive approximation type) 10-bit resolution, 8 channels successive approximation type: conversion time of 5.6 m s at 25 mhz internal sample and hold circuit conversion mode: single conversion/scanning conversion/repeated conversion selective start: software/external trigger/internal timer selective reload timer 16-bit timer: 2 channels internal clock: 2 clock cycle resolution, divide by 2/8/32 selective pin input: event counter input/gate function square wave output up/down counter 16-bit timer: 2 channels timer mode/up/down counter mode/phase shift count mode pin input activates counter clear/gate function other interval timers 16-bit timer: 2 channels (u-timer), 1 channel (free run for icu/ocu) watch-dog timer: 1 channel input capture/output compare capture: 4 channels, compare: 8 channels count can be cleared on compare match 16-bit uni?d free-run timer embedded bit search module first bit transition ??? from msb can be detected in 1 cycle interrupt controller external interrupt input: non-maskable interrupt (nmi ), normal interrupt 8 (int0 to int7) internal interrupt incident: parity error, uart, dmac, a/d, reload timer, up/down counter, capture/compare, baud rate timer, extended serial i/o, free-run timer and delayed interrupt priority levels of interrupts are programmable in 16 steps (except for non-maskable interrupt) others reset cause: power-on reset/hardware standby/watch-dog timer/software reset/external reset low power consumption mode sleep mode/stop mode clock gear function operating clocks for cpu and peripherals are independently selective gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) package qfp-160 cmos technology (0.65 m m), operating voltage 5.0 v 10%
MB91103 series 4 n product lineup product items MB91103 mb91v100 data cache none max. 4 kb (4 kb/2 kb/1 kb/512 b selective) instruction cache 1 kb ?ed max. 4 kb (4 kb/2 kb/1 kb/512 b selective) dmac 5 channels (ch. 0, 1, 4, 5 and 6 only) address register (32-bit length) 2 (dmaar 0,1) address register (16-bit length) 6 (dmaar 2 to 7) transfer count register (16-bit length) 2 (dmact 0, 1) transfer count register (8-bit length) 3 (dmact 4 to 6) channels for cycle steal operation: 2 channels (ch. 0, 1) 19 internal transfer causes 8 channels 32-bit length 4 (dmaar 0 to 3) 16-bit length 4 (dmaar 4 to 7) 16-bit length 4 (dmact 0 to 3) 8-bit length 4 (dmact 4 to 7) 4 channels (ch. 0 to 3) 23 internal interrupt causes u-timer 2 channels 3 channels uart 2 channels 3 channels d/a converter 2 channels incorporated external interrupts 8 channels (int0 to int7) 12 channels (int0 to int11) a/d converter successive approximation type only successive approximation type serial-parallel type timer units incorporated dsp unit incorporated pin conditions in each state pg 4 to pg 7 are ?ed to 0 when cpu stops con?ured as input when cpu stops
5 MB91103 series n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 d00/p00 d01/p01 d02/p02 d03/p03 d04/p04 d05/p05 d06/p06 d07/p07 v ss d08/p10 d09/p11 d10/p12 d11/p13 v cc d12/p14 d13/p15 d14/p16 d15/p17 v ss d16/p20 d17/p21 d18/p22 d19/p23 v cc d20/p24 d21/p25 d22/p26 d23/p27 d24 d25 d26 d27 v ss d28 d29 d30 d31 a00 a01 a02 so0/pe5 si0/pe4 int3/pe3 int2/pe2 int1/pe1 int0/pe0 v ss an7/pd7 an6/pd6 an5/pd5 an4/pd4 av ss avrl avrh av cc an3/pd3 an2/pd2 an1/pd1 an0/pd0 nmi hst md2 md1 md0 dw1/pb7 dw0/pb6 cs1h/pb5 cs1l/pb4 v cc cs0h/pb3 cs0l/pb2 ras1/pb1 ras0/pb0 v ss clk/pa6 cs5/pa5 cs4/pa4 cs3/pa3 cs2/pa2 cs1/pa1 (top view) (fpt-160p-m03) 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 a03 a04 a05 a06 a07 v cc a08 a09 a10 a11 v ss a12 a13 a14 a15 a16/p60 a17/p61 a18/p62 a19/p63 a20/p64 a21/p65 a22/p66 a23/p67 rdy/p80 bgrnt/p81 brq/p82 rd wr0 wr1/p85 wr2/p86 wr3/p87 aclk/p90 v ss ale/p91 par0/p92 par1/p93 v cc par2/p94 par3/p95 cs0/pa0 v cc x1 x0 v ss rst oc7/pi3 oc6/pi2 oc5/pi1 oc4/pi0 oc3/ph7 v ss oc2/ph6 oc1/ph5 oc0/ph4 ic3/zin1/ph3 ic2/bin1ph2 ic1/ain1/ph1 ic0/sc2/zin0/ph0 to1/bin0/pg7 ti1/ain0/pg6 v cc to0pg5 ti0/pg4 dreq1/int7/pg3 dreq0/pg2 dack1/int6/atg/pg1 dack0/pg0 n.c. pf7 pf6 n.c. int5/pf5 int4/pf4 v ss so2/pf3 si2/pf2 sc1/pf1 so1/pf0 si1/pe7 sc0/pe6 index note: no connections to n.c. pins.
MB91103 series 6 n pin description * : fpt-160p-m03 (continued) pin no. pin name circuit type function qfp* 158 x0 a clock (oscillator) input 159 x1 clock (oscillator) output 97 to 99 md0 to md2 g mode pins 0 to 2 input pins for operation mode speci?ation. directly connect these pins with v cc or v ss for use. 156 rst b external reset input. 1 to 8 d00 to d07 j bit 0 to bit 7 of external data bus. p00 to p07 i/o port. this function is available when external data bus width is set to 8-bit or 16-bit. 10 to 13, 15 to 18 d08 to d15 j bit 8 to bit 15 of external data bus. p10 to p17 i/o port. this function is available when external data bus width is set to 8-bit or 16-bit. 20 to 23, 25 to 28 d16 to d23 j bit 16 to bit 23 of external data bus. p20 to p27 i/o port. this function is available when external data bus width is set to 8-bit. 29 to 32, 34 to 37 d24 to d31 j bit 24 to bit 31 of external data bus. 38 to 45, 47 to 50, 52 to 55 a00 to a15 c bit 0 to bit 15 of external address bus. 56 to 63 a16 to a23 c bit 16 to bit 23 of external address bus. p60 to p67 can be con?ured as i/o ports when not used as address bus. 64 rdy j external ready input. outputs ? level bus cycle is being executed and not completed. p80 can be con?ured as i/o port. 65 bgrnt c external bus release acknowledge output. outputs ? level when external bus is released. p81 can be con?ured as i/o port. 66 brq j external bus release request input. input ? level when release of external bus is required. p82 can be con?ured as i/o port. 67 rd c read strobe output pin for external bus. 68 wr0 c write strobe output pin for external bus.
7 MB91103 series (continued) * : fpt-160p-m03 (continued) pin no. pin name circuit type function qfp* 69 to 71 wr1 to wr3 c write strobe output pin for external bus. relation between control signals and effective byte locations is as follows: p85 to p87 can be con?ured as i/o port. 72 aclk c clock output for a bus cycle. p90 can be con?ured as i/o port. 74 ale c address strobe signal in time-sharing mode. p91 can be con?ured as i/o port. 75, 76, 78, 79 par0 to par3 j parity input/output. relation between control signals and effective byte locations is as follows: p92 to p95 can be con?ured as i/o port. 80 to 85 cs0 to cs5 c chip select 0 to 5 output. (? active) pa0 to pa5 can be con?ured as i/o port. 86 clk c system clock output. outputs clock signal of internal operating frequency. pa6 can be con?ured as i/o port. 88 ras0 c ras output for dram bank 0. pb0 can be con?ured as i/o port. 89 ras1 c ras output for dram bank 1. pb1 can be con?ured as i/o port. 90 cs0l c casl output for dram bank 0. pb2 can be con?ured as i/o port. 91 cs0h c cash output for dram bank 0. pb3 can be con?ured as i/o port. 93 cs1l c casl output for dram bank 1. pb4 can be con?ured as i/o port. 8-bit bus width wr0 (i/o port enabled) (i/o port enabled) (i/o port enabled) 32-bit bus width wr0 wr1 wr2 wr3 d31 to d24 d23 to d16 d15 to d08 d07 to d00 16-bit bus width wr0 wr1 (i/o port enabled) (i/o port enabled) 32-bit bus width par0 par1 par2 par3 d31 to d24 d23 to d16 d15 to d08 d07 to d00 16-bit bus width par0 par1 (i/o port enabled) (i/o port enabled) 8-bit bus width par0 (i/o port enabled) (i/o port enabled) (i/o port enabled)
MB91103 series 8 (continued) * : fpt-160p-m03 (continued) pin no. pin name circuit type function qfp* 94 cs1h c cash output for dram bank 1. pb5 can be con?ured as i/o port. 95 d w0 cwe output for dram bank 0. (? active) pb6 can be con?ured as i/o port. 96 d w1 cwe output for dram bank 1. (? active) pb7 can be con?ured as i/o port. 100 hst h hardware standby input pin. (? active) 101 nmi h nmi (non-maskable interrupt pin) input pin. (? active) 102 to 105 an0 to an3 d analog input pins of a/d converter. this function is available when aic register is set to specify analog input mode. pd0 to pd3 general-purpose i/o ports. this function is available when aic register is set to con?ure i/o ports. 110 to 113 an4 to an7 d analog input pins of a/d converter. this function is available when aic register is set to specify analog input mode. pd4 to pd7 general-purpose i/o ports. this function is available when aic register is set to con?ure i/o ports. 115 to 118 int0 to int3 i external interrupt request input pins. this pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. int0 and int1 can be used as a dma request when dmac is so con?ured. pe0 to pe3 general-purpose i/o port. 119 si0 f data input pin for extended serial i/o interface (sio). this pin is used for input during sio is in operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pe4 general-purpose i/o port. 120 so0 c data output for extended serial i/o interface (sio). this function is available when serial data output speci?ation of sio is enabled. pe5 general-purpose i/o port. this function is available when serial data output of extended serial i/o interface (sio) is disabled. 121 sc0 f clock input/output pin for extended serial i/o interface. clock output is valid when clock output of sio is enabled. pe6 general-purpose i/o port. this function is available when clock output of sio is enabled.
9 MB91103 series (continued) * : fpt-160p-m03 (continued) pin no. pin name circuit type function qfp* 122 si1 f uart0 data input pin. this pin is used for input during uart0 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pe7 general-purpose i/o port. 123 so1 c uart0 data output pin. this function is available when uart0 data output is enabled. pf0 general-purpose i/o port. this function is available when serial data output of uart0 is disabled. 124 sc1 f uart0 clock i/o pin. this function is available when uart0 clock output is enabled. pf1 general-purpose i/o port. this function is available when uart0 clock output is disabled. 125 si2 f uart1 data input pin. this pin is used for input during uart1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pf2 general-purpose i/o port. 126 so2 c uart1 data output pin. this function is available when uart1 data output is enabled. pf3 general-purpose i/o port. this function is available when uart1 data output is disabled. 128, 129 int4, int5 i external interrupt request input pins. these pins are used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. pf4, pf5 general-purpose i/o ports. 131, 132 pf6, pf7 e i/o ports of open-drain type. 134 dack0 c transfer request acknowledge output pin for dmac (ch. 0). this function is available when transfer request output for dmac is enabled. pg0 general-purpose i/o port. this function is available when transfer request for dmac is disabled.
MB91103 series 10 (continued) * : fpt-160p-m03 (continued) pin no. pin name circuit type function qfp* 135 dack1 i external transfer request acknowledge output pin for dmac (ch. 1). this function is available when transfer request output for dmac is enabled. int6 external interrupt request input pins. this pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. a tg external trigger input pin for a/d converter. this pin is used for input when external trigger is selected to cause a/d converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pg1 general-purpose i/o port. this function is available when transfer request acknowledge for dmac is disabled. 136 dreq0 f external transfer request input pin for dma (ch. 0). this pin is used for input when external trigger is selected to cause dmac operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pg2 general-purpose i/o port. 137 dreq1 i external transfer request input pin for dma (ch. 1). this pin is used for input when external trigger is selected to cause dmac operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. int7 external interrupt request input pins. this pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pg3 general-purpose i/o port. 138 ti0 f input pin for reload-timer 0. this pin is used for input when input to reload-timer 0 is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pg4 general-purpose i/o port. 139 to0 f output pin for reload-timer 0. this function is available when output from reload-timer is enabled. pg5 general-purpose i/o port. this function is available when output from reload-timer is disabled.
11 MB91103 series (continued) * : fpt-160p-m03 (continued) pin no. pin name circuit type function qfp* 141 ti1 f input pin for reload-timer 1. this pin is used for input when input to reload-timer is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. ain0 ain input for up/down counter 0. this pin is used for input when input to the counter is enabled in phase-shift count mode or up/down count mode, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pg6 general-purpose i/o port. 142 t01 f input pin for reload-timer 1. this pin is used for input when input to reload-timer is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. bin0 bin input for up/down counter 0. this pin is used for input when input to the counter is enabled in phase-shift count mode or up/down count mode, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pg7 general-purpose i/o port. this function is available when output from reload-timer is disabled. 143 ic0 f input pin for input capture 0 (icu0). this pin is used for input when icu is in edge detect operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. sc2 clock i/o pin for uart1. this function is available when cock output of uart1 is enabled. zin0 zin-input for up/down counter 0. this pin is used for input when zin-input to the counter is enabled in by up/down counter 0, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. ph0 general purpose i/o port. this function is available when clock output of uart1 is enabled. 144 ic1 f input pin for input capture 1 (icu1). this pin is used for input when icu is in edge detect operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. ain1 ain input for up/down counter 1. this pin is used for input when input to the counter is enabled in phase-shift count mode or up/down count mode, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. ph1 general-purpose i/o port.
MB91103 series 12 (continued) * : fpt-160p-m03 (continued) pin no. pin name circuit type function qfp* 145 ic2 f input pin for input capture 2 (icu2). this pin is used for input when icu is in edge detect operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. bin1 bin input for up/down counter 1. this pin is used for input when input to the counter is enabled in phase-shift count mode or up/down count mode, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. ph2 general-purpose i/o port. 146 ic3 f input pin for input capture 3 (icu3). this pin is used for input when icu is in edge detect operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. zin1 zin-input for up/down counter 1. this pin is used for input when zin-input to the counter is enabled by up/down counter 1, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. ph3 general-purpose i/o port. 147 oc0 k output pin for output compare 0 (ocu0). this function is available when output of corresponding ocu is enabled. ph4 general-purpose i/o port. this function is available when output of corresponding ocu is disabled. 148 oc1 k output pin for output compare 1 (ocu1). this function is available when output of corresponding ocu is enabled. ph5 general-purpose i/o port. this function is available when output of corresponding ocu is disabled. 149 oc2 k output pin for output compare 2 (ocu2). this function is available when output of corresponding ocu is enabled. ph6 general-purpose i/o port. this function is available when output of corresponding ocu is disabled. 151 oc3 k output pin for output compare 3 (ocu3). this function is available when output of corresponding ocu is enabled. ph7 general-purpose i/o port. this function is available when output of corresponding ocu is disabled.
13 MB91103 series (continued) * : fpt-160p-m03 note: in most of the above pins, i/o port and resource i/o are multiplexed e.g. p82 and brq. in case of con?ct between output of i/o port and resource i/o, priority is always given to the output of resource i/o. pin no. pin name circuit type function qfp* 152 oc4 k output pin for output compare 4 (ocu4). this function is available when output of corresponding ocu is enabled. pi0 general-purpose i/o port. this function is available when output of corresponding ocu is disabled. 153 oc5 k output pin for output compare 5 (ocu5). this function is available when output of corresponding ocu is enabled. pi1 general-purpose i/o port. this function is available when output of corresponding ocu is disabled. 154 oc6 k output pin for output compare 6 (ocu6). this function is available when output of corresponding ocu is enabled. pi2 general-purpose i/o port. this function is available when output of corresponding ocu is disabled. 155 oc7 f output pin for output compare 7 (ocu7). this function is available when output of corresponding ocu is enabled. pi3 general-purpose i/o port. this function is available when output of corresponding ocu is disabled. 130, 133 n.c. no connections allowed to this pin. 14, 24 46, 77 92, 140 160 v cc power supply pin (v cc ) for digital circuit 9, 19 33, 51 73, 87 114, 127 150, 157 v ss earth level (v ss ) for digital circuit. 106 av cc power supply pin (v cc ) for a/d converter. 107 avrh reference voltage input (high) for a/d converter. make sure to turn on and off this pin with potential of avrh or more applied to v cc . 108 avrl reference voltage input pin (low) for a/d converter. 109 av ss power supply pin (v ss ) for a/d converter.
MB91103 series 14 n dram control pin *1: 0, 1, 2 and 3 respectively corresponds to the lowest 2 bits of address as follows: 0: ?0? 1: ?1? 2: ?0? 3: ?1 *2: l and h respectively corresponds to the lsb of address as follows: l: ?? h: ? pin name data bus 32-bit mode data bus 16-bit mode data bus 8-bit mode 2cas/1we mode 1cas/2we mode 2cas/1we mode 1cas/2we mode ras0 area 4 ras area 4 ras area 4 ras area 4 ras area 4 ras ras1 area 5 ras area 5 ras area 5 ras area 5 ras area 5 ras cs0l cas0 * 1 cas area 4 casl * 2 area 4 cas area 4 cas cs0h cas1 * 1 cas area 4 cash * 2 area 4 wel * 2 area 4 cas cs1l cas2 * 1 we0 * 1 area 5 casl * 2 area 5 cas area 5 cas cs1h cas3 * 1 we1 * 1 area 5 cash * 2 area 5 wel * 2 area 5 cas d w0 we we2 * 1 area 4 we area 4 weh * 2 area 4 we d w1 we we3 * 1 area 5 we area 5 weh * 2 area 5 we
15 MB91103 series n i/o circuit type (continued) type circuit remarks a oscillation feedback resistance 1 m w approx. with standby control b cmos level hysteresis input without standby control with pull-up resistance c cmos level i/o with standby control d cmos level i/o with standby control analog input x1 x0 standby control signal clock input v ss pch. r pch. nch. v cc digital input r standby control signal digital input digital output digital output pch. nch. r standby control signal digital input analog input digital output digital output pch. nch.
MB91103 series 16 (continued) (continued) type circuit remarks e n-channel open-drain output cmos level output with standby control f cmos level output cmos level hysteresis input with standby control g cmos level i/o without standby control h cmos level hysteresis input without standby control r pch. nch. standby control signal digital input digital output r pch. nch. standby control signal digital input digital output r pch. nch. digital input r pch. nch. digital input
17 MB91103 series (continued) type circuit remarks i cmos level output cmos level hysteresis input without standby control j cmos level output ttl level input with standby control k cmos level input/output with standby control large current drive r pch. nch. digital input digital output digital output r pch. nch. ttl standby control signal digital input digital output digital output r pch. nch. standby control signal digital input digital output digital output
MB91103 series 18 n handling devices 1. preventing latchup in cmos ics, applying voltage higher than v cc or lower than v ss to input/output pin or applying voltage over rating across v cc and v ss may cause latchup. this phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. make sure to prevent the voltage from exceeding the maximum rating. for the same reason, make sure to prevent the analog power supply voltage (av cc , avr) and analog input from exceeding the digital power supply voltage when turning on/off the device. 2. treatment of unused pins unused pins left open may cause malfunctions. make sure to connect them to pull-up or pull-down resistors. 3. remarks for external clock operation when external clock is selected, stabilization time is necessary at the time of power reset (optional) or wakening up from stop mode. 4. power supply pins when there are several v cc and v ss pins, each of them is geometrically connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. to further reduce the risk of malfunctions, to prevent emi radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect each pin directly to v cc or v ss outside of the device. it is preferred to connect v cc and v ss of this device to power supply with minimal impedance possible. it is also recommended to connect a bypass capacitor of about 0.1 m f between v cc and v ss at a position as close as possible to this device. 5. crystal oscillator circuit noises around x0 and x1 pins may cause malfunctions of this device. in designing the pc board, lay out x0, x1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. prevent their wiring from being crossed by other wires. it is strongly recommended to design pc board so that x1 and x0 pins are surrounded by grounding area for stable operation. x0 x1 MB91103
19 MB91103 series 6. turning-on sequence of a/d converter power supply and analog input make sure to turn on the digital power supply (v cc ) before turning on the a/d converter (av cc , avrh, avrl) and applying voltage to analog input (an0 to an7). make sure to turn off digital power supply after power supply to a/d converters and analog inputs have been switched off. (there are no such limitations in turning on power supplies. analog and digital power supplies may be turned on simultaneously.) make sure that avrh never exceeds av cc when turning on/off power supplies. 7. treatment of n.c. pins make sure to leave n.c. (internal connection) pins open. 8. fluctuation of power supply voltage warranty range for normal operation against ?ctuation of power supply voltage is as given in rating. however, sudden ?ctuation of power supply voltage within the warranty range may cause malfunctions. it is recommended to make every effort to stabilize the power supply voltage. 9. mode setting pins connect mode setting pins (md0 to md2) directly to v cc or v ss . arrange each mode setting pin and v cc or v ss patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises. 10. external reset input keep the rst pin level at ? for at least 5 machine cycles to ensure proper reset operation. 11. hst pin keep the hst pin level at ? when turning on the device. do not make the hst pin level at ? when rst pin level is at ??
MB91103 series 20 n block diagram bit search module instruction cache d bus (32-bit) i bus (16-bit) c bus (32-bit) r bus (16-bit) clock control unit interrupt control unit a/d converter (8 ch.) reload timer (2 ch.) pd0 to pd7 pe0 to pe7 pf0 to pf5 pg0 to pg7 ph0 to ph7 pi0 to pi3 ain0 ain1 bin0 bin1 zin0 zin1 up-down counter port d to port i 8 8 6 8 8 4 bus converter (32-bit ? 16-bit) dram controller port 0 to port b uart (2 ch.) u-timer (2 ch.) (baud rate timer) bus controller dmac (5 ch.) bus converter (harvard ? princeton) extended i/o serial interface real-time i/o time fr20 cpu ti0 ti1 to0 to1 x0 x1 rst hst dreq0 dreq1 dack0 dack1 d00 to d31 a00 to a23 rd wr0 to wr3 rdy aclk clk ale par0 to par3 cs0 to cs5 brq bgrnt p00 to p07 p10 to p17 p20 to p27 p60 to p67 p80 to p82 p85 to p87 p90 to p95 pa0 to pa6 pb0 to pb7 si1 si2 so1 so2 sc1 sc2 si0 so0 sc0 ic0 to ic3 oc0 to oc7 int0 to int7 nmi an0 to an7 atg av cc av ss avrh avrl 8 8 8 8 4 ras0 ras1 cs0l cs0h cs1l cs1h dw0 dw1 8 3 3 8 8 8 8 6 4 4 24 32 v cc , v ss , md0 to md2 other pins 8
21 MB91103 series n cpu core 1. memory space the fr20 series has a logical address space of 4 g bytes (2 32 bytes) and the cpu linearly accesses the memory space. the MB91103 has no internal memories (ram, rom). direct addressing area the following areas on the memory space are assigned to direct addressing area for i/o. in these areas, an address can be speci?d in a direct operand of a code. direct areas consists of the following areas dependent on accessible data sizes. byte data access: 0 to 0ff h half word data access: 0 to 1ff h word data access: 0 to 3ff h i/o area i/o area access inhibited external area external area direct addressing area see n i/o map 0000 0000 h 0000 0400 h 0000 0800 h 0001 0000 h 000c 0000 h ffff ffff h memory space
MB91103 series 22 2. registers the fr20 series has two types of registers -- dedicated registers embedded on the cpu and general-purpose registers on memory. dedicated registers program counter (pc) : 32-bit length, indicates the location of the instruction to be executed program status (ps) : 32-bit length, register for storing register pointer or condition codes table base register (tbr) : holds top address of vector table used in eit (exceptional/interrupt/trap) processing. return pointer (rp) : holds address to resume operation after returning from a subroutine. system stack pointer (ssp) : indicates system stack space. user's stack pointer (usp) : indicates users stack space. multiplication/division result register (mdh/mdl): 32-bit length, register for multiplication/division. the ps register is for holding program status and consists of a condition code register (ccr), a system condition code register (scr) and a level mask register (ilm). pc ps tbr rp ssp usp mdh mdl initial value program counter program status table base register return pointer system stack pointer users stack pointer multiplication/division result register xxxx xxxx h not fixed 000f fc00 h xxxx xxxx h not fixed 0000 0000 h xxxx xxxx h not fixed xxxx xxxx h not fixed xxxx xxxx h not fixed 32 bit ilm4 ilm3 ilm2 ilm1 ilm0 d1 d0 t s zc v n i 31 20 19 18 17 16 10 9 8 7 5 620 1 3 4 ilm scr ccr ps
23 MB91103 series condition code register (ccr) s ?g : speci?s a stack pointer used as r15. i ?g : controls user interrupt request enable/disable. n ?g : indicates sign bit when division result is assumed to be in the 2s complement format. z ?g : indicates whether or not the result of division was ?? v ?g : assume the operand used in calculation in the 2s complement format and indicates whether or not over?w has occurred. c ?g : indicates if a carry or borrow from the msb has occurred. system condition code register (scr) t ?g : speci?s whether or not to enable step trace trap. interrupt level mask register (ilm) ilm4 to ilm0 : register for holding interrupt level mask value. the value held by this register is used as a level mask. when an interrupt request issued to the cpu is higher than the level held by ilm, the interrupt request is accepted. ilm4 ilm3 ilm2 ilm1 ilm0 interrupt level priority 00000 0 high : : : : 01000 15 : : : : 11111 31 low
MB91103 series 24 n general-purpose registers r0 to r15 are general-purpose registers embedded on the cpu. these registers functions as an accumulator and a memory access pointer (?ld for indicating address). user can specify the functions of the registers. of the above 16 registers, following registers have special functions. to support the special functions, part of the instruction set has been sophisticated to have enhanced functions. r13: virtual accumulator (ac) r14: frame pointer (fp) r15: stack pointer (sp) upon reset, values in r0 to r14 are not ?ed. value in r15 is initialized to be 00000000 h (ssp value). register bank structure r0 r1 r12 r13 r14 r15 ac (accumulator) fp (frame pointer) sp (stack pointer) 32-bit : : initial value xxxx xxxx h : : : : : : : : : : : xxxx xxxx h 0000 0000 h
25 MB91103 series n setting mode 1. pin mode setting pins and modes * : MB91103 does not support single-chip mode. 2. registers mode setting registers and modes bus mode setting bits and functions note: for a device without internal rom, set ?0 b only. MB91103 allows ?0 b setting only. mode setting pins mode name reset vector access area external data bus width bus mode md2 md1 md0 0 0 0 external vector mode 0 external 8 bits external rom external bus mode 0 0 1 external vector mode 1 external 16 bits 0 1 0 external vector mode 2 external 32 bits 0 1 1 internal vector mode internal (mode register) single-chip mode* 1 inhibited m1 m0 functions note 0 0 single-chip mode 0 1 internal rom external bus mode 1 0 external rom external bus mode 1 1 inhibited m1 m0 ** * *** address 0000 07ff h bus mode setting bit w : write only x : not ?ed * : always write "0" to m1 and m0. initial value xxxx xxxx b access w
MB91103 series 26 n i/o map (continued) address register name (abbreviated) register name write/read initial value 0000 h vacant 0001 h pdr2 port 2 data register r/w xxxxxxxx b 0002 h pdr1 port 1 data register r/w xxxxxxxx b 0003 h pdr0 port 0 data register r/w xxxxxxxx b 0004 h vacant 0005 h pdr6 port 6 data register r/w xxxxxxxx b 0006 h vacant 0007 h 0008 h pdrb port b data register r/w xxxxxxxx b 0009 h pdra port a data register r/w xxxxxxx b 000a h pdr9 port 9 data register r/w xxxxxx b 000b h pdr8 port 8 data register r/w x x x x x x b 000c h to 0010 h vacant 0011 h pdrd port d data register r/w xxxxxxxx b 0012 h pdre port e data register r/w xxxxxxxx b 0013 h pdrf port f data register r/w xxxxxxxx b 0014 h pdrg port g data register r/w xxxxxxxx b 0015 h pdrh port h data register r/w xxxxxxxx b 0016 h pdri port i data register r/w xxxx b 0017 h vacant 0018 h 0019 h sdr serial data register r/w xxxxxxxx b 001a h smcs serial mode control status register r/w 00000010 b 001b h 0000 b 001c h ssr0 serial status register 0 r/w 00001?0 b 001d h sidr0/sodr0 serial input register 0/serial output register 0 r/w xxxxxxxx b 001e h scr0 serial control register 0 r/w 00000100 b 001f h smr0 serial mode register 0 r/w 000?0 b 0020 h ssr1 serial status register 1 r/w 00001?0 b 0021 h sidr1/sodr1 serial input register 1/serial output register 1 r/w xxxxxxxx b 0022 h scr1 serial control register 1 r/w 00000100 b
27 MB91103 series (continued) (continued) address register name (abbreviated) register name write/read initial value 0023 h smr1 serial mode register 1 r/w 000?0 b 0024 h to 0027 h vacant 0028 h tmrlr0 16-bit reload register ch. 0 w xxxxxxxx b 0029 h xxxxxxxx b 002a h tmr0 16-bit timer register ch. 0 r xxxxxxxx b 002b h xxxxxxxx b 002c h vacant 002d h 002e h tmcsr0 16-bit reload timer control status register ch. 0 r/w 0000 b 002f h 00000000 b 0030 h tmrlr1 16-bit reload register ch. 1 w xxxxxxxx b 0031 h xxxxxxxx b 0032 h tmr1 16-bit timer register ch. 1 r xxxxxxxx b 0033 h xxxxxxxx b 0034 h vacant 0035 h 0036 h tmcsr1 16-bit reload timer control status register ch. 1 r/w 0000 b 0037 h 00000000 b 0038 h adcr a/d converter data register r 000000xx b 0039 h xxxxxxxx b 003a h adcs a/d converter control status register r/w 00000000 b 003b h 00000000 b 003c h to 0044 h vacant 0045 h ics0 input capture control status register ch. 0 r/w 00000000 b 0046 h vacant 0047 h 0048 h ipcp0 input capture data register 0 r xxxxxxxx b 0049 h xxxxxxxx b 004a h ipcp1 input capture data register 1 r xxxxxxxx b 004b h xxxxxxxx b
MB91103 series 28 (continued) (continued) address register name (abbreviated) register name write/read initial value 004c h vacant 004d h ics1 input capture control status register ch. 1 r/w 00000000 b 004f h vacant 004e h 0050 h ipcp2 input capture data register 2 r xxxxxxxx b 0051 h xxxxxxxx b 0052 h ipcp3 input capture data register 3 r xxxxxxxx b 0053 h xxxxxxxx b 0054 h ocs0 output compare control status register ch. 0 r/w ?0000 b 0055 h 000000 b 0056 h vacant 0057 h 0058 h opcp0 output compare register ch. 0 r/w xxxxxxxx b 0059 h xxxxxxxx b 005a h opcp1 output compare register ch. 1 r/w xxxxxxxx b 005b h xxxxxxxx b 005c h ocs1 output compare control status register ch. 1 r/w ?0000 b 005d h 000000 b 005e h vacant 005f h 0060 h opcp2 output compare register ch. 2 r/w xxxxxxxx b 0061 h xxxxxxxx b 0062 h opcp3 output compare register ch. 3 r/w xxxxxxxx b 0063 h xxxxxxxx b 0064 h ocs2 output compare control status register ch. 2 r/w ?0000 b 0065 h 000000 b 0066 h vacant 0067 h 0068 h opcp4 output compare register ch. 4 r/w xxxxxxxx b 0069 h xxxxxxxx b 006a h opcp5 output compare register ch. 5 r/w xxxxxxxx b 006b h xxxxxxxx b
29 MB91103 series (continued) (continued) address register name (abbreviated) register name write/read initial value 006c h ocs3 output compare control status register ch. 3 r/w ?0000 b 006d h 000000 b 006e h vacant 006f h 0070 h opcp6 output compare register ch. 6 r/w xxxxxxxx b 0071 h xxxxxxxx b 0072 h opcp7 output compare register ch. 7 r/w xxxxxxxx b 0073 h xxxxxxxx b 0074 h tcdt 16-bit free-run timer count data register r/w 00000000 b 0075 h 00000000 b 0076 h vacant 0077 h tccs 16-bit free-run timer count control status register r/w 00000000 b 0078 h utim0/utimr0 u-timer register ch. 0/reload register ch. 0 r/w 00000000 b 0079 h 00000000 b 007a h vacant 007b h utimc0 u-timer control register ch. 0 r/w 000001 b 007c h utim1/utimr1 u-timer register ch. 1/reload register ch. 1 r/w 00000000 b 007d h 00000000 b 007e h vacant 007f h utimc1 u-timer control register ch. 1 r/w 000001 b 0080 h to 0083 h vacant 0084 h udcr0 16-bit up-down count register ch. 0 r 00000000 b 0085 h 00000000 b 0086 h rcr0 16-bit up/down counter reload/compare register ch. 0 w 00000000 b 0087 h 00000000 b 0088 h ccr0 16-bit up/down counter control register ch. 0 r/w ?000000 b 0089 h ?001000 b 008a h vacant 008b h csr0 16-bit up/down counter status register ch. 0 r/w 00000000 b 008c h udcr1 16-bit up/down count register ch. 1 r 00000000 b 008d h 00000000 b
MB91103 series 30 (continued) (continued) address register name (abbreviated) register name write/read initial value 008e h rcr1 16-bit up/down counter reload/compare register ch. 1 w 00000000 b 008f h 00000000 b 0090 h ccr1 16-bit up/down counter control register ch. 1 r/w ?000000 b 0091 h ?001000 b 0092 h vacant 0093 h csr1 16-bit up/down counter status register ch. 1 r/w 00000000 b 0094 h eirr external interrupt cause register r/w 00000000 b 0095 h enir interrupt enable register r/w 00000000 b 0096 h vacant 0097 h 0098 h elvr external interrupt request level setting register r/w 00000000 b 0099 h 00000000 b 009a h to 00d0 h vacant 00d1 h ddrd port d data direction register w 00000000 b 00d2 h ddre port e data direction register w 00000000 b 00d3 h ddrf port f data direction register w 00000000 b 00d4 h ddrg port g data direction register w 00000000 b 00d5 h ddrh port h data direction register w 00000000 b 00d6 h ddri port i data direction register w 0000 b 00d7 h aic port d analog input control register w 00000000 b 00d8 h to 01ff h vacant 0200 h dmacs0 dmac-ch. 0 control/status register r/w 0?00000 b 0201 h 000x0 b 0202 h xxxxxxxx b 0203 h xxxxxxxx b 0204 h dmacc0 dmac-ch. 0 addressing/count setting register r/w xxxxxxxx b 0205 h xxxxxxx b 0206 h xxxxxxxx b 0207 h xxxxxxxx b
31 MB91103 series (continued) (continued) address register name (abbreviated) register name write/read initial value 0208 h dmacs1 dmac-ch. 1 control/status register r/w 0?00000 b 0209 h 000x0 b 020a h xxxxxxxx b 020b h xxxxxxxx b 020c h dmacc1 dmac-ch. 1 addressing/count setting register r/w xxxxxxxx b 020d h xxxxxxx b 020e h xxxxxxxx b 020f h xxxxxxxx b 0210 h to 021f h vacant 0220 h dmacs4 dmac-ch. 4 control/status register r/w 0?00000 b 0221 h 000 b 0222 h xxxxxx b 0223 h xxxx b 0224 h dmacc4 dmac-ch. 4 addressing/count setting register r/w 0000 xxxx b 0225 h xxxxxxx b 0226 h xxxxxxxx b 0227 h xxxxxxxx b 0228 h dmacs5 dmac-ch. 5 control/status register r/w 0?00000 b 0229 h 000 b 022a h xxxxxx b 022b h xxxx b 022c h dmacc5 dmac-ch. 5 addressing/count setting register r/w 0000 xxxx b 022d h xxxxxxx b 022e h xxxxxxxx b 022f h xxxxxxxx b 0230 h dmacs6 dmac-ch. 6 control/status register r/w 0?00000 b 0231 h 000 b 0232 h xxxxxx b 0233 h xxxx b
MB91103 series 32 (continued) (continued) address register name (abbreviated) register name write/read initial value 0234 h dmacc6 dmac-ch. 6 addressing/count setting register r/w 0000 xxxx b 0235 h xxxxxxx b 0236 h xxxxxxxx b 0237 h xxxxxxxx b 0238 h to 023f h vacant 0240 h dmaar0 dmac address register 0 r/w xxxxxxxx b 0241 h xxxxxxxx b 0242 h xxxxxxxx b 0243 h xxxxxxxx b 0244 h dmaar1 dmac address register 1 r/w xxxxxxxx b 0245 h xxxxxxxx b 0246 h xxxxxxxx b 0247 h xxxxxxxx b 0248 h dmaar2 dmac address register 2 r/w 00000000 b 0249 h 00000xxx b 024a h xxxxxxxx b 024b h xxxxxxxx b 024c h dmaar3 dmac address register 3 r/w 00000000 b 024d h 00000xxx b 024e h xxxxxxxx b 024f h xxxxxxxx b 0250 h dmaar4 dmac address register 4 r/w 00000000 b 0251 h 00000xxx b 0252 h xxxxxxxx b 0253 h xxxxxxxx b 0254 h dmaar5 dmac address register 5 r/w 00000000 b 0255 h 00000xxx b 0256 h xxxxxxxx b 0257 h xxxxxxxx b
33 MB91103 series (continued) (continued) address register name (abbreviated) register name write/read initial value 0258 h dmaar6 dmac address register 6 r/w 00000000 b 0259 h 00000xxx b 025a h xxxxxxxx b 025b h xxxxxxxx b 025c h dmaar7 dmac address register 7 r/w 00000000 b 025d h 00000xxx b 025e h xxxxxxxx b 025f h xxxxxxxx b 0260 h dmact0 dmac transfer count register 0 r/w xxxxxxxx b 0261 h xxxxxxxx b 0262 h dmact1 dmac transfer count register 1 r/w xxxxxxxx b 0263 h xxxxxxxx b 0264 h to 0267 h vacant 0268 h dmact4 dmac transfer count register 4 r/w 00000000 b 0269 h xxxxxxxx b 026a h dmact5 dmac transfer count register 5 r/w 00000000 b 026b h xxxxxxxx b 026c h dmact6 dmac transfer count register 6 r/w 00000000 b 026d h xxxxxxxx b 026e h to 0273 h vacant 0274 h dmacr dmac total control register r/w b 0275 h b 0276 h 00 b 0277 h 0000 b 0278 h to 03e3 h vacant 03e4 h ichcr instruction cache control register r/w b 03e5 h b 03e6 h b 03e7 h 000000 b
MB91103 series 34 (continued) (continued) address register name (abbreviated) register name write/read initial value 03e8 h to 03ef h vacant 03f0 h bsd0 bit search module 0-detection data register w xxxxxxxx b 03f1 h xxxxxxxx b 03f2 h xxxxxxxx b 03f3 h xxxxxxxx b 03f4 h bsd1 bit search module 1-detection data register r/w xxxxxxxx b 03f5 h xxxxxxxx b 03f6 h xxxxxxxx b 03f7 h xxxxxxxx b 03f8 h bsdc bit search module transition-detection data register w xxxxxxxx b 03f9 h xxxxxxxx b 03fa h xxxxxxxx b 03fb h xxxxxxxx b 03fc h bsrr bit search module detection result register r xxxxxxxx b 03fd h xxxxxxxx b 03fe h xxxxxxxx b 03ff h xxxxxxxx b 0400 h icr00 interrupt control register 0 r/w ?1111 b 0401 h icr01 interrupt control register 1 r/w ?1111 b 0402 h icr02 interrupt control register 2 r/w ?1111 b 0403 h icr03 interrupt control register 3 r/w ?1111 b 0404 h icr04 interrupt control register 4 r/w ?1111 b 0405 h icr05 interrupt control register 5 r/w ?1111 b 0406 h icr06 interrupt control register 6 r/w ?1111 b 0407 h icr07 interrupt control register 7 r/w ?1111 b 0408 h icr08 interrupt control register 8 r/w ?1111 b 0409 h icr09 interrupt control register 9 r/w ?1111 b 040a h icr10 interrupt control register 10 r/w ?1111 b 040b h icr11 interrupt control register 11 r/w ?1111 b 040c h icr12 interrupt control register 12 r/w ?1111 b 040d h icr13 interrupt control register 13 r/w ?1111 b
35 MB91103 series (continued) (continued) address register name (abbreviated) register name write/read initial value 040e h icr14 interrupt control register 14 r/w ?1111 b 040f h icr15 interrupt control register 15 r/w ?1111 b 0410 h icr16 interrupt control register 16 r/w ?1111 b 0411 h icr17 interrupt control register 17 r/w ?1111 b 0412 h icr18 interrupt control register 18 r/w ?1111 b 0413 h icr19 interrupt control register 19 r/w ?1111 b 0414 h icr20 interrupt control register 20 r/w ?1111 b 0415 h icr21 interrupt control register 21 r/w ?1111 b 0416 h icr22 interrupt control register 22 r/w ?1111 b 0417 h icr23 interrupt control register 23 r/w ?1111 b 0418 h icr24 interrupt control register 24 r/w ?1111 b 0419 h icr25 interrupt control register 25 r/w ?1111 b 041a h icr26 interrupt control register 26 r/w ?1111 b 041b h icr27 interrupt control register 27 r/w ?1111 b 041c h icr28 interrupt control register 28 r/w ?1111 b 041d h icr29 interrupt control register 29 r/w ?1111 b 041e h icr30 interrupt control register 30 r/w ?1111 b 041f h icr31 interrupt control register 31 r/w ?1111 b 0420 h icr32 interrupt control register 32 r/w ?1111 b 0421 h icr33 interrupt control register 33 r/w ?1111 b 0422 h icr34 interrupt control register 34 r/w ?1111 b 0423 h icr35 interrupt control register 35 r/w ?1111 b 0424 h icr36 interrupt control register 36 r/w ?1111 b 0425 h icr37 interrupt control register 37 r/w ?1111 b 0426 h icr38 interrupt control register 38 r/w ?1111 b 0427 h icr39 interrupt control register 39 r/w ?1111 b 0428 h icr40 interrupt control register 40 r/w ?1111 b 0429 h icr41 interrupt control register 41 r/w ?1111 b 042a h icr42 interrupt control register 42 r/w ?1111 b 042b h icr43 interrupt control register 43 r/w ?1111 b 042c h icr44 interrupt control register 44 r/w ?1111 b 042d h icr45 interrupt control register 45 r/w ?1111 b
MB91103 series 36 (continued) (continued) address register name (abbreviated) register name write/read initial value 042e h icr46 interrupt control register 46 r/w ?1111 b 042f h icr47 interrupt control register 47 r/w ?1111 b 0430 h dicr delayed interrupt control register r/w ? b 0431 h hrcl hold request cancel request level setting register r/w ?1111 b 0432 h to 047f h vacant 0480 h rsrr/wtcr reset cause register/watch-dog peripheral control register r/w 1xxxx 0 0 b 0481 h stcr standby control register r/w 000111 b 0482 h pdrr dma request squelch register r/w 0000 b 0483 h ctbr time-base timer clear register w xxxxxxxx b 0484 h gcr gear control register r/w 1111? b 0485 h wpr watch-dog reset occurrence postpone register w xxxxxxxx b 0486 h to 0600 h vacant 0601 h ddr2 port 2 data direction register w 00000000 b 0602 h ddr1 port 1 data direction register w 00000000 b 0603 h ddr0 port 0 data direction register w 00000000 b 0604 h vacant 0605 h ddr6 port 6 data direction register w 00000000 b 0606 h vacant 0607 h 0608 h ddrb port b data direction register w 00000000 b 0609 h ddra port a data direction register w ?000000 b 060a h ddr9 port 9 data direction register w 000000 b 060b h ddr8 port 8 data direction register w 000000 b 060c h asr1 area select register 1 w 00000000 b 060d h 00000001 b 060e h amr1 area mask register 1 w 00000000 b 060f h 00000000 b 0610 h asr2 area select register 2 w 00000000 b 0611 h 00000010 b
37 MB91103 series (continued) (continued) address register name (abbreviated) register name write/read initial value 0612 h amr2 area mask register 2 w 00000000 b 0613 h 00000000 b 0614 h asr3 area select register 3 w 00000000 b 0615 h 00000011 b 0616 h amr3 area mask register 3 w 00000000 b 0617 h 00000000 b 0618 h asr4 area select register 4 w 00000000 b 0619 h 00000100 b 061a h amr4 area mask register 4 w 00000000 b 061b h 00000000 b 061c h asr5 area select register 5 w 00000000 b 061d h 00000101 b 061e h amr5 area mask register 5 w 00000000 b 061f h 00000000 b 0620 h amd0 area mode register 0 r/w ?0111 b 0621 h amd1 area mode register 1 r/w 000000 b 0622 h amd32 area mode register 32 r/w 00000000 b 0623 h amd4 area mode register 4 r/w 000000 b 0624 h amd5 area mode register 5 r/w 000000 b 0625 h dscr dram signal control register w 00000000 b 0626 h rfcr refresh control register r/w xxxxxx b 0627 h 00?00 b 0628 h epcr0 external pin control register 0 w ?001100 b 0629 h ?111111 b 062a h epcr1 external pin control register 1 w b 062b h 11111111 b 062c h dmcr4 dram control register 4 r/w 00000000 b 062d h 0000000 b 062e h dmcr5 dram control register 5 r/w 00000000 b 062f h 0000000 b 0630 h to 07fd h vacant
MB91103 series 38 (continued) note: do not use vacant areas. n interrupt causes, interrupt vectors and interrupt control register allocations (continued) address register name (abbreviated) register name write/read initial value 07fe h ler little endian register w ?00 b 07ff h modr mode register w xxxxxxxx b interrupt causes interrupt number interrupt level * 1 interrupt vector * 2 decimal hexa- decimal setting register register address offset vector address reset * 1 0 00 3fc h 000ffffc h reserved for system 1 01 3f8 h 000ffff8 h reserved for system 2 02 3f4 h 000ffff4 h reserved for system 3 03 3f0 h 000ffff0 h reserved for system 4 04 3ec h 000fffec h reserved for system 5 05 3e8 h 000fffe8 h reserved for system 6 06 3e4 h 000fffe4 h co-processor unattended trap 7 07 3e0 h 000fffe0 h co-processor error trap 8 08 3dc h 000fffdc h inte instruction 9 09 fixed to 4 3d8 h 000fffd8 h instruction break exception 10 0a 3d4 h 000fffd4 h operand break trap 11 0b 3d0 h 000fffd0 h step trace trap 12 0c fixed to 4 3cc h 000fffcc h reserved for system 13 0d 3c8 h 000fffc8 h exception for unde?ed instruction 14 0e 3c4 h 000fffc4 h nmi (user) request 15 0f fixed to 15 (f h ) 3c0 h 000fffc0 h parity error area 4 16 10 icr00 00000400 h 3bc h 000fffbc h parity error area 5 17 11 icr01 00000401 h 3b8 h 000fffb8 h external interrupt 0 18 12 icr02 00000402 h 3b4 h 000fffb4 h external interrupt 1 19 13 icr03 00000403 h 3b0 h 000fffb0 h external interrupt 2 20 14 icr04 00000404 h 3ac h 000fffac h external interrupt 3 21 15 icr05 00000405 h 3a8 h 000fffa8 h external interrupt 4 22 16 icr06 00000406 h 3a4 h 000fffa4 h external interrupt 5 23 17 icr07 00000407 h 3a0 h 000fffa0 h external interrupt 6 24 18 icr08 00000408 h 39c h 000fff9c h
39 MB91103 series (continued) (continued) interrupt causes interrupt number interrupt level * 1 interrupt vector * 2 decimal hexa- decimal setting register register address offset vector address external interrupt 7 25 19 icr09 00000409 h 398 h 000fff98 h reserved for system 26 1a icr10 0000040a h 394 h 000fff94 h uart0 receive complete 27 1b icr11 0000040b h 390 h 000fff90 h uart1 receive complete 28 1c icr12 0000040c h 38c h 000fff8c h reserved for system 29 1d icr13 0000040d h 388 h 000fff88 h uart0 transmit complete 30 1e icr14 0000040e h 384 h 000fff84 h uart1 transmit complete 31 1f icr15 0000040f h 380 h 000fff80 h reserved for system 32 20 icr16 00000410 h 37c h 000fff7c h dmac0 (complete, error) 33 21 icr17 00000411 h 378 h 000fff78 h dmac1 (complete, error) 34 22 icr18 00000412 h 374 h 000fff74 h reserved for system 35 23 icr19 00000413 h 370 h 000fff70 h reserved for system 36 24 icr20 00000414 h 36c h 000fff6c h dmac4 (complete, error) 37 25 icr21 00000415 h 368 h 000fff68 h dmac5 (complete, error) 38 26 icr22 00000416 h 364 h 000fff64 h dmac6 (complete, error) 39 27 icr23 00000417 h 360 h 000fff60 h reserved for system 40 28 icr24 00000418 h 35c h 000fff5c h a/d (successive approximation type) 41 29 icr25 00000419 h 358 h 000fff58 h reload timer 0 42 2a icr26 0000041a h 354 h 000fff54 h reload timer 1 43 2b icr27 0000041d h 350 h 000fff50 h u/d counter 0 44 2c icr28 0000041c h 34c h 000fff4c h u/d counter 1 45 2d icr29 0000041d h 348 h 000fff48 h icu0 46 2e icr30 0000041e h 344 h 000fff44 h icu1 47 2f icr31 0000041f h 340 h 000fff40 h icu2 48 30 icr32 00000420 h 33c h 000fff3c h icu3 49 31 icr33 00000421 h 338 h 000fff38 h ocu0 50 32 icr34 00000422 h 334 h 000fff34 h ocu1 51 33 icr35 00000423 h 330 h 000fff30 h ocu2 52 34 icr36 00000424 h 32c h 000fff2c h ocu3 53 35 icr37 00000425 h 328 h 000fff28 h ocu4 54 36 icr38 00000426 h 324 h 000fff24 h ocu5 55 37 icr39 00000427 h 320 h 000fff20 h
MB91103 series 40 (continued) *1: icr sets an interrupt level corresponding to the interrupt request into a register provided in the interrupt controller. icr is provided for each interrupt request. *2: vector addresses are given by adding an offset value corresponding to each eit (exception/interrupt/trap) cause to the tbr value. tbr (table base register) holds the top address of eit vector table. default value (initial value upon reset 000ffc00 h ) is used in n interrupt causes, interrupt vectors and interrupt control register allocations. interrupt causes interrupt number interrupt level * 1 interrupt vector * 2 decimal hexa- decimal setting register register address offset vector address ocu6 56 38 icr40 00000428 h 31c h 000fff1c h ocu7 57 39 icr41 00000429 h 318 h 000fff18 h u-timer 0 58 3a icr42 0000042a h 314 h 000fff14 h u-timer 1 59 3b icr43 0000042b h 310 h 000fff10 h reserved for system 60 3c icr44 0000042c h 30c h 000fff0c h i/o extended serial 61 3d icr45 0000042d h 308 h 000fff08 h 16-bit free-run timer 62 3e icr46 0000042e h 304 h 000fff04 h delayed interrupt cause bit 63 3f icr47 0000042f h 300 h 000fff00 h reserved for system (used in realos * 2 ) 64 40 2fc h 000ffefc h reserved for system (used in realos * 2 ) 65 41 2f8 h 000ffef8 h used in int instructions 66 to 255 42 to ff 2f4 h to 000 h 000ffef4 h to 000ffd00 h
41 MB91103 series n peripheral resources 1. i/o ports there are 2 types of i/o port register structure ?port data register (pdr0 to pdri) and data direction register (ddr0 to ddri, aic), where bits pdr0 to pdr i and bits ddr0 to ddri corresponds respectively. each bit on the register corresponds to an external pin. in port registers input/output register of the port con?ures input/ output function of the port, while corresponding bit (pin) con?ures input/output function in data direction registers. bit ? speci?s input and ? speci?s output. for input (ddr = ?? setting; pdr reading operation: reads level of corresponding external pin pdr writing operation: writes set value to pdr pdr ddr (port data register) (data direction register) resource output enable resource output 1 0 1 0 pdr read resource input pin data bus block diagram
MB91103 series 42 access type(s) in parenthesis r/w : read and write access type w : write only - : vacant x : not ?ed * : a/d converter input/general-purpose input port selective by port d input pdr0 pdr1 pdr2 pdr6 pdr8 pdr9 pdra pdrb pdrd pdre pdrf pdrg pdrh pdri bit 7 bit 0 port data register 000003 h 000002 h 000001 h 000005 h 00000b h 00000a h 000009 h 000008 h 000011 h 000012 h 000013 h 000014 h 000015 h 000016 h xxxxxxxx b (r/w) xxxxxxxx b (r/w) xxxxxxxx b (r/w) xxxxxxxx b (r/w) xxx- - xxx b (r/w) - - xxxxxx b (r/w) - xxxxxxx b (r/w) xxxxxxxx b (r/w) xxxxxxxx b (r/w) xxxxxxxx b (r/w) xxxxxxxx b (r/w) xxxxxxxx b (r/w) xxxxxxxx b (r/w) - - - - xxxx b (r/w) address initial value data direction register ddr0 ddr1 ddr2 ddr6 ddr8 ddr9 ddra ddrb ddrd ddre ddrf ddrg ddrh ddri aic* bit 7 bit 0 000603 h 000602 h 000601 h 000605 h 00060b h 00060a h 000609 h 000608 h 0000d1 h 0000d2 h 0000d3 h 0000d4 h 0000d5 h 0000d6 h 0000d7 h 00000000 b (w) 00000000 b (w) 00000000 b (w) 00000000 b (w) 000- - 000 b (w) - - 000000 b (w) - 0000000 b (w) 00000000 b (w) 00000000 b (w) 00000000 b (w) 00000000 b (w) 00000000 b (w) 00000000 b (w) - - - - 0000 b (w) 00000000 b (w) address initial value
43 MB91103 series 2. dma controller (dmac) the dma controller is a module embedded in fr 20 series devices, and performs dma (direct memory access) transfer. dma transfer performed by the dma controller transfers data without intervention of cpu, contributing to enhanced performance of the system. input setting register external input setting external transfer request input request setting register setting request for each channel external transfer input transfer request processing request for each channel request arbitration priority judgment transfer ch. decision control mode setting register priority setting for each channel setting transfer mode for each channel channel setting register address control register address generation control for each channel hold control hold request transfer start request transfer state machine (bus control) specified i/o i/o access control fixed address generation address counter address/count count control transfer count counter interrupt control address register group data control count register group data buffe fr20 cpu ack d-bus peripheral interrupt request peripheral interrupt request dreq0 dreq1 : : ch. specification complete count address block diagram
MB91103 series 44 bit 31 bit 16 bit 0 bit 31 bit 0 registers 00000200 h 00000204 h 00000208 h 0000020c h 00000220 h 00000224 h 00000228 h 0000022c h 00000230 h 00000234 h 00000240 h 00000244 h 00000248 h 0000024c h 00000250 h 00000254 h 00000258 h 0000025c h 00000260 h 00000262 h 00000268 h 0000026a h 0000026c h 00000274 h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w address access *1: 32-bit length, ? upper 16 bits except for the least-signi?ant 3 bits to ?? *2: 16-bit length, ? upper 8 bits to ?? *3: 16-bit length, ? lower 8 bits to ?? fixed 00000000 00000 b xxx b bit 8 bit 16 bit 0 fixed 00000000 b bit 8 bit 16 bit 0 fixed 00000000 b dmact0 dmact4 * 2 dmact6 * 2 dmact1 dmact5 * 3 bit 16 dmacs0 dmacc0 dmacs1 dmacc1 dmacs4 dmacc4 dmacs5 dmacc5 dmacs6 dmacc6 dmaar0 dmaar1 dmaar2 * 1 dmaar3 * 1 dmaar4 * 1 dmaar5 * 1 dmaar6 * 1 dmaar7 * 1 dmacr * 1
45 MB91103 series 3. uart the uart is a serial i/o port for supporting asynchronous (start-stop system) communication or clk synchronous communication. the MB91103 consists of 2 channels of uart. control signals from external clock si (receive data) clock select circuit receive interrupt (to cpu) transmit interrupt (to cpu) receive control circuit start bit detect circuit receive bit counter receive parity counter transmit control circuit transmit start circuit transmit bit counter transmit parity counter receive status judge circuit receive shifter receive complete transmit shifter transmit start receive error generate signal for dma (to dmac) sidr sodr r ?bus smr register md1 md0 cs0 scke soe scr register ssr register control signals transmit clock receive clock so (transmit data) pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sc (clock) from u-timer sci block diagram
MB91103 series 46 4. i/o extended serial interface this block is a serial interface of 8-bit 1 structure enabling clock synchronous data transfer. data transfer format of lsb ?st or msb ?st can be selected. dma transfer operation is enabled by interrupt request. there are two serial i/o operating modes. internal shift clock mode : in this mode, data transfer operation is synchronized with internal clock. it can be selected from 10/20/80/160/320 frequency division of machine clock. external shift clock mode : in this mode, data transfer operation is synchronized with clock input from external pin (sc0). data transfer by cpu instructions is enabled when the general port sharing the external pin (sc0) is so con?ured. bit 15 bit 0 registers 0000001e h 00000022 h 0000001f h 00000023 h 0000001c h 00000020 h 0000001d h 00000021 h (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) address initial value scr0 scr1 ssr0 ssr1 smr0 smr1 sidr0/sodr0 sidr1/sidr1 bit 8 access type(s) in parenthesis r/w : read and write access type : vacant x : not ?ed 00000100 b 00000100 b 00- -0-00 b 00- -0-00 b 00001 - 00 b 00001 - 00 b xxxxxxxx b xxxxxxxx b
47 MB91103 series control circuit shift clock counter internal clock transfer direction select read write interrupt request smcs si0 so0 sc0 sdr (serial data register) 10 2 smd2 smd1 smd0 sir sie busy stop strt mode bds soe scoe (msb first) d0 to d7 d7 to d0 (lsb first) r ?bus r ?bus block diagram bit 15 bit 0 registers 0000001a h 00000019 h (r/w) (r/w) (r/w) address initial value smcs sdr bit 8 access type(s) in parenthesis r/w : read and write access type : vacant x : not ?ed 00000010 b ---- 0000 b xxxxxxxx b
MB91103 series 48 5. u-timer (16-bit timer for uart baud rate generation) the u-timer is a 16-bit timer for generating uart baud rate. combination of chip operating frequency and reload value of u-timer allows ?xible setting of baud rate. the u-timer operates as an interval timer by using interrupt issued on counter under?w. the MB91103 has 2 channel u-timer embedded on the chip. by combining 2 interval timers in cascade, an interval of up to 2 32 f can be counted. u-timer (reload register) 15 0 utim ( u-timer register) 15 0 clock underflow ch. 0 only underflow to uart f (peripheral clock) mux control f.f. load block diagram bit 15 bit 0 registers 00000078 h 0000007c h 0000007b h 0000007f h (r/w) (r/w) (r/w) (r/w) address initial value utimc0 utimc1 access type(s) in parenthesis r/w : read and write access type : vacant x : not ?ed utim0/utimr0 utim1/utimr1 00000000 b 00000000 b 00000000 b 00000000 b 0 - - 00001 b 0 - - 00001 b
49 MB91103 series 6. 16-bit reload timer the 16-bit timer consists of a 16-bit down counter, a 16-bit reload timer, a pre-scaler for generating internal count clock and control registers. internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock) or external clock. the input/output pin (to) outputs a deleted toggle wave on every under?w in the reload mode and outputs a square wave indicating the timer is in counting operation in the one-shot mode. the input pin (ti) is con?ured as an event input in the event count mode, a trigger input in the internal clock mode and also operates as a gate input. the external event count function in the reload mode can operate as a external clock divider. the MB91103 consists of 2 channels of 16-bit reload timer. tmrlr 0, 1 (16-bit reload register) 16-bit down counter uf clock selector reload reld oute outl inte uf cnte trg out ctl. csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 in ctl. f 2 f 2 f 2 135 3 internal clock pre-scaler clear exck gate 2 retrigger irq port (ti) tmcsr1 port (to) tmcr0 tmcr0 r-bus block diagram
MB91103 series 50 7. real time input/output timer the 16-bit input/output timer consists of a 16-bit free-run timer, 8 output compares and 4 input capture modules. by using these functions, 8 independent wave outputs based on the 16-bit free-run timer as well as input pulse width measurement and external clock cycle measurement can be realized. bit 15 bit 0 registers 0000002e h 00000036 h 0000002a h 00000032 h 00000028 h 00000030 h ---- 0000 b 00000000 b ---- 0000 b 00000000 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b address initial value access type(s) in parenthesis r/w : read and write type r : read only w : write only : vacant x : not ?ed (r/w) (r/w) (r) (r) (w) (w) tmcsr0 tmcsr1 tmr0 tmr1 tmrlr0 tmrlr1
51 MB91103 series control logic input capture 1 input capture 0 output compare 3 output compare 2 output compare 1 output compare 0 16-bit free-run timer 16-bit timer compare register 0 compare register 1 compare register 2 compare register 3 compare register 4 compare register 5 compare register 6 capture register 0 capture register 1 capture register 2 capture register 3 compare register 7 toggle output toggle output oc0 oc1 toggle output toggle output oc2 oc3 toggle output toggle output oc4 oc5 toggle output toggle output oc6 oc7 edge select ic0 edge select ic1 edge select ic2 edge select ic3 clear interrupt 13 r-bus to each block block diagram
MB91103 series 52 (1) 16-bit free-run timer the 16-bit free-run timer consists of a 16-bit up/down counter and a control status register. count value of this timer is used in output compare and input capture blocks as a basic time. count clock can be selected from 4 types of frequencies ( f /4, f /16, f /32, f /64). interrupt can be issued upon count over?w. selecting a mode and setting the count value as equaling to the value of compare register ? initializes the counter. interrupt request ivf ivfe stop mode clr clk1 clk0 divider f comparator 0 clock t15 to t00 count value output 16-bit up counter tccs r-bus block diagram bit 15 bit 0 registers 00000074 h 00000077 h 00000000 b 00000000 b 00000000 b address initial value tcdt bit 8 access type(s) in parenthesis r/w : read and write access type tccs (r/w) (r/w)
53 MB91103 series (2) output compare the output compare consists of a 16-bit compare register, compare output pin block and a control register. when the value set in the compare register matches with the 16-bit free-run timer value, output level is reversed, enabling an interrupt request to be issued. 8 compare registers can operate independently. a pair of compare registers can be used for controlling output pin levels. initial output level of output pins can be speci?d. an interrupt is issued when compare value matches with timer value. compare control compare register 0 (2 ch., 4 ch., 6 ch.) (opcpo0, 1) 16-bit timer counter value (t15 to t00) compare control compare register 1 (3 ch., 5 ch., 7 ch.) (opcp2, 3) 16-bit timer counter value (t15 to t00) to each control block control block toggle output ote0 oc0 cmod toggle output ote1 icp1 icp0 ice1 ice0 oc1 ocs compare 0 interrupt compare 1 interrupt combinations of compare register 0 and 1: ch.0, ch.1/ch.2, ch.3/ch.4, ch.5/ch.6, ch.7 r-bus block diagram
MB91103 series 54 bit 15 bit 0 registers 00000058 h 0000005a h 00000060 h 00000062 h 00000068 h 0000006a h 00000070 h 00000072 h 00000054 h 0000005c h 00000064 h 0000006c h address initial value access type(s) in parenthesis r/w : read and write access type : vacant x : not fixed (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) opcp0 opcp1 opcp2 opcp3 opcp4 opcp5 opcp6 opcp7 ocs0 ocs1 ocs2 ocs1 xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b - - - 00000 b 0000 - - 00 b - - - 00000 b 0000 - - 00 b - - - 00000 b 0000 - - 00 b - - - 00000 b 0000 - - 00 b
55 MB91103 series (3) input capture the input capture consists of input capture data registers and input capture control status registers. the input capture detects a rising edge, a falling edge or both edges of external input signal and hold the 16-bit free-run timer value at the moment into the register. the input capture can issue an interrupt upon edge detection, if enabled. every input capture has a corresponding output pin. effective edge of external input can be selected from rising, falling or both edges. the input capture issues an interrupt upon detection of an effective edge, if enabled. 16-bit timer counter value (t15 to t00) input capture data register 0, 2 (ipcp0, 2) 16-bit timer counter value (t15 to t00) input capture data register 1, 3 (ipcp1, 3) edge detect ico eg11 eg10 eg01 eg00 ics1 ic1 edge detect icp1 icp0 ice1 ice0 interrupt interrupt r-bus block diagram bit 15 bit 0 registers 00000048 h 0000004a h 00000050 h 00000052 h 00000045 h 0000004d h xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 00000000 b 00000000 b address initial value access type(s) in parenthesis r/w : read and write access type r : read only x : not fixed ics0 ics1 ipcp0 ipcp1 ipcp2 ipcp3 (r) (r) (r) (r) (r/w) (r/w) bit 8
MB91103 series 56 8. up/down counter the up/down counter consists of 3 event input pins, a 16-bit up/down counter, 16-bit reload/compare register and peripheral circuits (control/status register) controlling these functions. the MB91103 consists of 2 channels of counter/timer. r ?bus rcr 0, 1 (reload/compare register) ctut reload control ucre rlde counter clear edge/level detect udcc udcr 0, 1 (up/down count register) cmpf udff ovff udie cms1 cms0 ces1 ces0 cge1 cge0 cgsc up/down count clock select pre-scaler clks udf1 cdcf cfie udf0 cite cstr convert direction over/underflow compare interrupt request ain bin zin ccr ccr count clock block diagram
57 MB91103 series bit 15 bit 0 registers 00000084 h 0000008c h 00000086 h 0000008e h 0000008b h 00000093 h 00000088 h 00000090 h 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b - 0000000 b - 0001000 b - 0000000 b - 0001000 b address initial value access type(s) in parenthesis r/w : read and write access type r : read only w : write only : vacant csr0 csr1 (r) (r) (w) (w) (r/w) (r/w) (r/w) (r/w) bit 8 udcr0 udcr1 rcr0 rcr1 ccr0 ccr1
MB91103 series 58 9. bit search module the bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. input latch single-detection data recovery bit search circuit search result address decoder detection mode d-bus block diagram bit 31 bit 0 registers 000003f0 h 000003f4 h 000003f8 h 000003fc h xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b address initial value access type(s) in parenthesis r/w : read and write access type r : read only w : write only (w) (r/w) (w) (r) bit 16 bsd0 bsd1 bsdc bsrr
59 MB91103 series 10. a/d converter the a/d converter converts an analog input voltage to a digital value. successive approximation register internal voltage generator av cc avr av ss mpx comparator analog input an0 an1 an2 an3 an4 an5 an6 an7 sample & hold circuit data register a/d control register pre-scaler adcr adcs operating clock atg trigger start tim0 (internal connection) (reload timer ch.0) timer start f (peripheral clock) r-bus input circuit decoder block diagram bit 15 bit 0 registers 0000003a h 00000038 h 00000000 b 00000000 b 000000xx b xxxxxxxx b address initial value access type(s) in parenthesis r/w : read and write access type r : read only x : not ?ed adcs adcr (r/w) (r)
MB91103 series 60 11. interrupt controller the interrupt controller processes interrupt acknowledgments and arbitration between interrupts. r ?bus level0* 4 im int0* 2 or priority judgment nmi nmi processing ri00 ri47 (dlyirq) dly1* 1 level judgment icr00 icr47 vector judgment 4 5 6 level vector generation hldreq cancel request level4 to hldcan* 3 vct0* 5 vct5 to block diagram *1: dly1 stands for delayed interrupt module (delayed interrupt generation block). *2: int0 is a wake-up signal to clock control block in the sleep or stop status. *3: hldcan is a bus release request signal for bus masters other than cpu. *4: level5 to level0 are interrupt level outputs. *5: vct5 to vct0 are interrupt vector outputs.
61 MB91103 series icr00 icr01 icr02 icr03 icr04 icr05 icr06 icr07 icr08 icr09 icr10 icr11 icr12 icr13 icr14 icr15 icr16 icr17 icr18 icr19 icr20 icr21 icr22 icr23 icr24 icr25 bit 7 bit 0 registers 00000400 h 00000401 h 00000402 h 00000403 h 00000404 h 00000405 h 00000406 h 00000407 h 00000408 h 00000409 h 0000040a h 0000040b h 0000040c h 0000040d h 0000040e h 0000040f h 00000410 h 00000411 h 00000412 h 00000413 h 00000414 h 00000415 h 00000416 h 00000417 h 00000418 h 00000419 h - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) address initial value access type(s) in parenthesis r/w : read and write access type : vacant icr26 icr27 icr28 icr29 icr30 icr31 icr32 icr33 icr34 icr35 icr36 icr37 icr38 icr39 icr40 icr41 icr42 icr43 icr44 icr45 icr46 icr47 hrcl dicr bit 7 bit 0 0000041a h 0000041b h 0000041c h 0000041d h 0000041e h 0000041f h 00000420 h 00000421 h 00000422 h 00000423 h 00000424 h 00000425 h 00000426 h 00000427 h 00000428 h 00000429 h 0000042a h 0000042b h 0000042c h 0000042d h 0000042e h 0000042f h 00000431 h 00000430 h - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - - - - - 0 b (r/w) address initial value
MB91103 series 62 12. external interrupt/nmi control block the external interrupt/nmi control block controls external interrupt request signals input to nmi and int0 to int 7 pins. detecting levels can be selected from ?? ?? rising edge and falling edge (not for nmi ). int1 and int0 can be used as a dma request signal. interrupt enable register (enir) interrupt cause register (eiir) request level setting register (elvr) gate cause f/f edge detection circuit interrupt request 8 8 8 9 9 int0 to int7 nmi r-bus block diagram bit 15 bit 0 registers 00000000 b 00000000 b 00000000 b 00000000 b address initial value enir elvr (r/w) (r/w) (r/w) bit 8 eirr access type(s) in parenthesis r/w : read and write access type 00000095 h 00000094 h 00000098 h
63 MB91103 series 13. clock generation/control block the clock generation/control block consists of the following 6 blocks: cpu clock generation (including gear function) peripheral clock generation (including gear function) reset generation and cause hold standby function (including hardware standby) dma request prohibit pll (duty ratio adjustment circuit included) gear control register (gcr) [clock generation/gear control block] cpu gear peripheral gear oscillator circuit x0 x1 1/2 pll generation circuit internal clock cpu clock internal bus clock peripheral dma clock internal peripheral clock [stop/sleep control block] internal interrupt request internal reset standby control register (stcr) control circuit status transition stop state sleep state cpu hold request internal reset reset generation f/f cpu hold enable hst pin dma request power on sel rst pin dma request prohibit register (pdrr) [dma prohibit circuit] reset cause register (rsrr) time-base timer count clock watch-dog cycle control register (wtcr) [watch-dog control block] time-base timer clear register (ctbr) watch-dog reset generation postpone register (wpr) r-bus selection circuit [reset cause circuit] block diagram
MB91103 series 64 14. dram controller the dram controller controls interface between cpu and dram. this function is active only when drme bit of amd4, amd5 are set to ?? the dmcr register also controls parity check functions. this function is active other than the dram interface. bit 15 bit 0 registers 1xxxx - 0 0 b 000111 - - b ---- 0000 b xxxxxxxx b 11 - - 11 - 1 b xxxxxxxx b address initial value bit 8 access type(s) in parenthesis r/w : read and write access type w : write only : vacant x : not ?ed 00000480 h 00000481 h 00000482 h 00000483 h 00000484 h 00000485 h stcr ctbr wpr rsrr/wtcr pdrr gcr (r/w) (r/w) (r/w) (w) (r/w) (w) bit 15 bit 0 registers 0000062c h 0000062e h 00000000 b 0000000 - b 00000000 b 0000000 - b address initial value access type(s) in parenthesis r/w : read and write access type : not used dmcr4 dmcr5 (r/w) (r/w)
65 MB91103 series n electrical characteristics 1. absolute maximum ratings (v ss = 0.0 v) *1: make sure that the voltage does not exceed v cc + 0.3 v. make sure av cc does not exceed v cc when turning on the device. *2: v i and v o must not exceed v cc + 0.3 v. *3: maximum output current is a peak current value measured at a corresponding pin. *4: average output current is an average current for a 100 ms period at a corresponding pin. *5: average total output current is an average current for a 100 ms period for all corresponding pins. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss ?0.3 v ss + 7.0 v analog supply voltage * 1 av cc v ss ?0.3 v ss + 7.0 v analog reference voltage * 1 avrh v ss ?0.3 v ss + 7.0 v analog reference voltage * 1 avrl v ss ?0.3 v ss + 7.0 v input voltage * 2 v i v ss ?0.3 v cc + 0.3 v output voltage * 2 v o v ss ?0.3 v cc + 0.3 v ? level maximum output current * 3 i ol ?0ma ? level average output current * 4 i olav ?ma ? level maximum total output current s i ol 100 ma ? level average total output current * 5 s i olav ?0ma ? level maximum output current * 3 i oh ?0 ma ? level average output current * 4 i ohav 4ma ? level maximum total output current s i oh ?0 ma ? level average total output current * 5 s i ohav ?0 ma power dissipation p d 990 mw operating temperature t a ?0 +70 c storage temperature tstg ?5 +150 c
MB91103 series 66 2. recommended operating conditions (v ss = 0.0 v) parameter symbol value unit remarks min. max. power supply voltage v cc 4.5 5.5 v normal operation 3.0 5.5 v retaining the ram state in stop mode analog supply voltage av cc v ss ?0.3 v cc + 0.3 v analog reference voltage avrh avrl av cc v avrl av ss avrh v operating temperature t a ?0 +70 c
67 MB91103 series warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the device? electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. 5.5 4.5 025 f cp /f cpp (mhz) 25 1.25 01025 50 f c (mhz) internal clock supply voltage 0.625 normal operation warranty range (t a = ?0 c to +70 c) v cc (v) divide-by-2 system pll system f cp /f cpp (mhz) 0.625 source oscillating clock internal clock note: use external clock if source oscillating clock > 25 mhz. pll oscillation stabilizing period > 100 m s
MB91103 series 68 3. dc characteristics (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) *1: hysteresis input pins :hst , nmi , pe0 to pe4, pe6, pe7, pf1, pf2, pf4, pf5, pg1 to pg3, ph0 to ph3, rst *2: ttl level input pins :d00 to d31, rdy, brq, par0 to par3 parameter symbol pin condition value unit remarks min. typ. max. ? level input voltage v ih input other than following symbols 0.7 v cc v cc + 0.3 v v ihs * 1 0.8 v cc v cc + 0.3 v hysteresis input v iht * 2 2.2 v cc + 0.3 v ttl level v ihm md0 to md2 v cc ?0.3 v cc + 0.3 v ? level input voltage v il input other than following symbols v ss ?0.3 0.3 v cc v v ils * 1 v ss ?0.3 0.2 v cc v hysteresis input v ilt * 2 v ss ?0.3 0.8 v ttl level v ilm md0 to md2 v ss ?0.3 v ss + 0.3 v open-drain output pin application voltage v d pf6, pf7 v ss ?0.3 v cc + 0.3 v ? level output voltage v oh d00 to d23 a00 to a31 p8 to pi (except for pf6, pf7) v cc = 4.5 v i oh = ?.0 ma 4.0 v ? level output voltage v ol1 d00 to d31 a00 to a23 p8 to pi (except for pf6, pf7) (except for ph4 to ph7) (except for pi0 to pi2) v cc = 4.5 v i ol = 8.0 ma 0.4 v v ol2 ph4 to ph7 pi0 to pi2 v cc = 4.5 v i ol = 12.0 ma 0.4 v v old pf6, pf7 v cc = 4.5 v i ol = 4.0 ma 0.4 v input leakage current (hi-z output leakage current) i li d00 to d31 a00 to a23 p8 to pi v cc = 5.5 v 0.45 v < v i < v cc 5 m a pull-up resistance r pull rst v cc = 5.5 v v i = 0.45 v 25 50 100 k w power supply current i cc v cc f c = 25 mhz v cc = 5.5 v 180 ma i ccs f c = 25 mhz v cc = 5.5 v 100 ma sleep mode input capacitance c in except for v cc , v ss , av cc , av ss ?0pf
69 MB91103 series 4. ac characteristics (1) clock timing rating (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) *1: frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system. *2: these values are for a minimum clock of 10 mhz input to x0, a divide-by-2 system of the source oscillation and a 1/8 gear. parameter symbol pin condition value unit remarks min. max. clock frequency f c x0 x1 10 50 mhz clock cycle time t c x0 x1 20 100 ns frequency shift ratio (when locked) * 1 d f 5% input clock pulse width p wh p wl x0 8.5 ns input clock rising/falling time t cr t cf x0 8 ns t cr + t cf internal operating clock frequency f cp 0.625 * 2 25 mhz cpu system f cpp 0.625 * 2 25 mhz peripheral system internal operating clock cycle time t cp ?0 1600 * 2 ns cpu system t cpp ?0 1600 * 2 ns peripheral system d f = 100 (%) | a | f 0 center frequency f 0 + a a + c = 80 pf output pin 0.8 v cc 0.2 v cc t cf t cr t c p wl p wh ac rating measurement conditions
MB91103 series 70 (2) clock output timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) *1: t cyc is a frequency for 1 clock cycle including a gear cycle. *2: this rating is for a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n of the following equations with 1/2, 1/4, 1/8, respectively. min. : (1 ?n/2) t cyc ?10 max. : (1 ?n/2) t cyc + 10 *3: this rating is for a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n of the following equations with 1/2, 1/4, 1/8, respectively. min. : n/2 t cyc ?10 max. : n/2 t cyc + 10 parameter symbol pin condition value unit remarks min. max. cycle time t cyc clk t cp ?s * 1 clk - ? clk t chcl clk 1/2 t cyc ?10 1/2 t cyc + 10 ns * 2 clk ? clk - t clch clk 1/2 t cyc ?10 1/2 t cyc + 10 ns * 3 clk 2.4 v 0.8 v 2.4 v t cyc t chcl t clch
71 MB91103 series the relation between x0 input and clock output for con?ured by chc/cck1/cck0 settings of gcr (gear control register) is as follows: t cyc t cyc t cyc t cyc t cyc t cyc t cyc t cyc x0 input (1) source oscillation x 1 (chc bit of gcr set to ?? (b) gear x 1/2 x clock output cck1/0: ?1 (c) gear x 1/4 clock output cck1/0: ?0 (d) gear x 1/8 clock output cck1/0: ?1 (2) source oscillation x 1/2 (chc bit of gcr set to ?? (a) gear x 1 clock output cck1/0: ?0 (b) gear x 1/2 clock output cck1/0: ?1 (c) gear x 1/4 clock output cck1/0: ?0 (d) gear x 1/8 clock output cck1/0: ?1 (a) gear x 1 clock output cck1/0: ?0
MB91103 series 72 discreet type *1: feed-back resistance rf internally connected in lsi. *2: no damping resistance required. ( ): c 1 and c 2 internally connected. frequency range [mhz] model circuit parameter contact type c1 [pf] c2 [pf] rf * 1 [ w ] rd * 2 [ w ] 10.00 to 13.00 csa mtz 30 30 0 2 contacts cst mtw (30) (30) 0 3 contacts 13.01 to 15.99 csa mxz040 15 15 0 2 contacts cst mxw0c3 (15) (15) 0 3 contacts 16.00 to 19.99 csa mxz040 10 10 0 2 contacts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 3 contacts 20.00 to 25.00 csa mxz040 5 5 0 2 contacts cst mxw0h1 (5) (5) 0 3 contacts c 2 c 1 * recommended circuit (2 contacts) x0 (158) x1 (159) recommended circuit (3 contacts) x0 (158) x1 (159) * c 1 c 2 c 1 , c 2 internally connected. * : murata mfg. co., ltd. ceramic oscillator applications
73 MB91103 series smd type *1: feed-back resistance rf internally connected in lsi. *2: no damping resistance required. ( ): c 1 and c 2 internally connected. (3) reset, hardware standby input (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) frequency range [mhz] model circuit parameter contact type c1 [pf] c2 [pf] rf * 1 [ w ] rd * 2 [ w ] 10.00 to 13.00 csacs mt 30 30 0 2 contacts cstcs mt (30) (30) 0 3 contacts 13.01 to 15.99 csacs mx040 15 15 0 2 contacts cstcs mx0c3 (15) (15) 0 3 contacts 16.00 to 19.99 csacs mx040 10 10 0 2 contacts cstcs mx0c2 (10) (10) 0 3 contacts 20.00 to 25.00 csacs mx040 5 5 0 2 contacts cstcs mx0h1 (5) (5) 0 3 contacts parameter symbol pin condition value unit remarks min. max. reset input time t rstl rst t cp 5 ns hardware standby input time t hstl hst t cp 5 ns rst hst 0.2 v cc t rstl , t hstl
MB91103 series 74 (4) power-on reset (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) parameter symbol pin condition value unit remarks min. max. power supply rising time t r v cc ?0ms v cc < 0.2 v before turning power supply power supply shut off time t off v cc 1ms for repeated operations oscillation stabilizing time t osc 2 t c 2 20 ?s 0.2 v t r 4.5 v v cc v ss 3 v 5 v ram data retention a voltage rising rate of 50 mv/ms or less is recommended. v cc rst v cc sudden change in supply voltage during operation may initiate a power-on sequence. to change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage. t rstl : reset input time set rst pin to "l" level when turning on the device, at least t rstl duration after the supply voltage reaches vcc is necessary before turning the rst to "h" level. t off t rstl t osc (oscillation stabilizing time)
75 MB91103 series (5) normal bus access read/write operation (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) *1: when bus timing is delayed by automatic wait insertion or rdy input, add (t cyc extended cycle number for delay) to this rating. *2: this rating is for a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. equation: (2 ?n/2) t cyc ?25 parameter symbol pin condition value unit remarks min. max. cs0 to cs5 delay time t chcsl clk cs0 to cs5 ?5ns t chcsh ?5ns address delay time t chav clk a23 to a00 ?5ns data (parity) delay time t chdv clk d31 to d00 par0 to par3 15 ns rd delay time t clrl clk rd 6ns t clrh 6ns wr0 to wr3 delay time t clwl clk wr0 to wr3 6ns t clwh 6ns valid address ? valid data (parity) input time t avdv a23 to a00 d31 to d00 par0 to par3 3/2 t cyc ?25 ns * 1 * 2 rd ? valid data (parity) input time t rldv rd d31 to d00 par0 to par3 t cyc ?10 ns * 1 data (parity) set up ? rd - time t dsrh 10 ns rd -? data (parity) hold time t rhdx 0ns
MB91103 series 76 2.4 v clk 0.8 v 2.4 v 0.8 v ba2 2.4 v t chcsl t chav 0.8 v 2.4 v 0.8 v t clrl 0.8 v t clwl 0.8 v t chdv 0.8 v 2.4 v write 0.8 v 2.4 v t clrh 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v t dsrh t rhdx t clwh 2.4 v read 2.4 v 0.8 v t chcsh 2.4 v cs0 to cs5 a23 to a00 rd d31 to d00 par0 to par3 wr0 to wr3 d31 to d00 par0 to par3 ba1 t cyc t rldv t avdv
77 MB91103 series (6) time-sharing bus read/write operation (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) * : when bus timing is delayed by automatic wait insertion or rdy input, add (t cyc extended cycle number for delay) to this rating. parameter symbol pin condition value unit remarks min. max. ale delay time t cllh clk ale ?ns t clll ?ns cs1 delay time t chcsl clk cs1 ?5ns t chcsh ?5ns address delay time t chav clk d31 to d16 ?5ns data delay time t chdv clk d31 to d16 ?5ns rd delay time t clrl clk rd 6ns t clrh 6ns wr0 , wr1 delay time t clwl clk wr0 , wr1 6ns t clwh 6ns rd ? valid data input time t rldv rd d31 to d16 t cyc ?10 ns * data set up ? rd - time t dsrh 10 ns rd -? data hold time t rhdx 0ns
MB91103 series 78 2.4 v 0.8 v clk 0.8 v 2.4 v ba1 ba2 2.4 v 2.4 v 2.4 v ma1 ma2 0.8 v 0.8 v 0.8 v t cllh 2.4 v 0.8 v t clll 0.8 v t chcsl t chav 0.8 v 2.4 v address 0.8 v 2.4 v t chav 0.8 v 2.4 v address t chav 0.8 v 2.4 v 0.8 v 2.4 v t chcsh 2.4 v write 0.8 v 2.4 v read t dsrh t rhdx 0.8 v 2.4 v t clrh t clrl 0.8 v 2.4 v 0.8 v 2.4 v t clwl t clwh ale cs1 read cycle d31 to d16 (multiplexed bus) rd write cycle d31 to d16 (multiplexed bus) wr0, wr1 a23 to a00 (non-multiplexed bus) t cyc t rldv t chdv
79 MB91103 series (7) ready input timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) parameter symbol pin condition value unit remarks min. max. aclk delay time t clakh clk aclk ?ns t clakl ?ns rdy set up time ? aclk - t rdys rdy aclk 10 ns aclk -? rdy hold time t rdyh aclk rdy 0ns clk 0.8 v 2.4 v 2.4 v 0.8 v t clakh 2.4 v 0.8 v aclk t clakl 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v t rdys t rdyh t rdys t rdyh rdy when wait(s) is inserted. rdy when no wait is inserted. t cyc
MB91103 series 80 (8) hold timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) note: there is a delay time of more than 1 cycle from brq input to bgrnt change. parameter symbol pin condition value unit remarks min. max. bgrnt delay time t chbgl clk bgrnt ?ns t chbgh ?ns pin ?ating ? bgrnt time t xhal bgrnt t cyc ?10 t cyc + 10 ns bgrnt -? pin valid time t hahv t cyc ?10 t cyc + 10 ns clk 2.4 v t chbgl 0.8 v each pin high impedance 2.4 v 2.4 v 2.4 v 2.4 v t chbgh brq bgrnt t cyc t xhal t hahv
81 MB91103 series (9) normal dram mode read/write cycle (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) cas: cs0l to cs1h pins are for cas signal outputs. d w :d w0 , d w1 and cs0h to cs1h are used for we outputs. *1: when q1 cycle or q4 cycle is extended for ? cycle, add t cyc time to this rating. *2: this rating is for a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute ? in the following equation with 1/2, 1/4, 1/8, respectively. equation: (3 ?n/2) t cyc ?16 parameter symbol pin condition value unit remarks min. max. ras delay time t clrah clk ras ?ns t chral ?ns cas delay time t clcasl clk cas ?ns t clcash ?ns row address delay time t chrav clk a23 to a00 ?5ns column address delay time t chcav ?5ns d w delay time t chdwl clk d w ?5ns t chdwh ?5ns output data (parity) delay time t chdv1 clk d31 to d00 par0 to par3 ?5ns ras ? valid data (parity) input time t rldv ras d31 to d00 par0 to par3 5/2 t cyc ?16 ns * 1 * 2 cas ? valid data (parity) input time t cldv cas d31 to d00 par0 to par3 ? cyc ?10 ns * 1 cas -? data (parity) hold time t cadh 0ns
MB91103 series 82 0.8 v 2.4 v write 0.8 v 2.4 v d31 to d00 par0 to par3 0.8 v 2.4 v column address 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v clk 0.8 v q2 q1 q3 q4 q5 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v t clrah t chral 0.8 v t clcash 2.4 v t clcash t chcav row address t chrav read 0.8 v 2.4 v 0.8 v 2.4 v t cadh 0.8 v 2.4 v t chdwl t chdwh t chdv1 d31 to d00 par0 to par3 ras cas a23 to a00 dw t cyc t rldv t cldv
83 MB91103 series (10) normal dram mode fast page read/write cycle (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) cas: cs0l to cs1h pins are for cas signal outputs. d w :d w0 , d w1 and cs0h to cs1h are used for we outputs. * : when q4 cycle is extended for 1 cycle, add t cyc time to this rating. parameter symbol pin condition value unit remarks min. max. ras delay time t clrah clk, ras ?ns cas delay time t clcasl clk cas ?ns t clcash ?ns column address delay time t chcav clk a23 to a00 ?5ns d w delay time t chdwh clk d w ?5ns output data (parity) delay time t chdv1 clk d31 to d00 par0 to par3 ?5ns cas ? valid data (parity) input time t cldv cas d31 to d00 par0 to par3 ? cyc ?10 ns * cas -? data (parity) hold time t cadh 0ns
MB91103 series 84 0.8 v 2.4 v column address 0.8 v 2.4 v t clcash t chcav column address column address 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v t chdwh t chdv1 write read read 0.8 v 2.4 v read d31 to d00 par0 to par3 clk d31 to d00 par0 to par3 ras cas a23 to a00 dw q4 q5 2.4 v 0.8 v q5 0.8 v q4 q5 2.4 v 0.8 v t clrah 2.4 v 2.4 v 0.8 v t clcasl 0.8 v 2.4 v t cadh write t cldv
85 MB91103 series (11) cbr refresh (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) cas: cs0l to cs1h pins are for cas signal outputs. parameter symbol pin condition value unit remarks min. max. ras delay time t clrah clk ras ?ns t chral ?ns cas delay time t clcasl clk cas ?ns t clcash ?ns t clcash clk ras cas 0.8 v 0.8 v r4 2.4 v 0.8 v t clrah r3 r2 r1 0.8 v 2.4 v 2.4 v 2.4 v 0.8 v t chral t clcasl dw t cyc
MB91103 series 86 (12) self refresh (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) cas: cs0l to cs1h pins are for cas signal outputs. parameter symbol pin condition value unit remarks min. max. ras delay time t clrah clk ras ?ns t chral ?ns cas delay time t clcasl clk cas ?ns t clcash ?ns clk ras cas 0.8 v t chral 2.4 v t clcasl t clrah 2.4 v sr2 2.4 v sr3 0.8 v 2.4 v 0.8 v sr3 0.8 v 2.4 v 2.4 v t clcash t cyc sr1
87 MB91103 series (13) uart timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) notes: this rating is for ac characteristics in clk synchronous mode. ? cycp is a cycle time of peripheral system clock. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc internal shift clock mode 8 t cycp ?s sclk ? sout delay time t slov ?0 80 ns valid sin ? sclk - t ivsh 100 ns sclk -? valid sin hold time t shix ?0ns serial clock ? pulse width t shsl external shift clock mode 4 t cycp ?s serial clock ? pulse width t slsh ? t cycp ?s sclk ? sout delay time t slov 150 ns valid sin ? sclk - t ivsh ?0ns sclk -? valid sin hold time t shix ?0ns sclk sout sin sclk sout sin t scyc t slov t ivsh t shix t shsl t slsh t slov t ivsh t shix internal shift clock mode external shift clock mode
MB91103 series 88 (14) i/o extended serial timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) note: t cycp is a cycle time of peripheral system clock. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc internal shift clock mode 8 t cycp ?s sclk ? sout delay time t slov 80 ns valid sin ? sclk - t ivsh ? t cycp ?s sclk -? valid sin hold time t shix ? t cycp ?s serial clock ? pulse width t shsl external shift clock mode 230 ns max. external frequency is 2 mhz serial clock ? pulse width t slsh 230 ns sclk ? sout delay time t slov 2 t cycp ns valid sin ? sclk - t ivsh ? t cycp ?s sclk -? valid sin hold time t shix ? t cycp ?s sclk sout sin sclk sout sin t scyc t slov t ivsh t shix t slsh t shsl t slov t ivsh t shix internal shift clock mode external shift clock mode
89 MB91103 series (15) timer system input timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) note: t cycp is a cycle time of peripheral system clock. (16) trigger system input timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) note: t cycp is a cycle time of peripheral system clock. parameter symbol pin condition value unit remarks min. max. input pulse width t tiwh t tiwl ti0, ti1 2 t cycp ?s parameter symbol pin condition value unit remarks min. max. a/d start trigger input time t atgx a tg 5 t cycp ?s input capture input trigger t inp ic0 to ic3 5 t cycp ?s t tiwh t tiwl atg ic0 to ic3 t atgx , t inp
MB91103 series 90 (17) up/down counter input timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) note: t cycp is a cycle time of peripheral system clock. parameter symbol pin condition value unit remarks min. max. ain input ? pulse width t ahl ain0 ain1 bin0 bin1 8 t cycp ?s ain input ? pulse width t all 8 t cycp ?s bin input ? pulse width t bhl 8 t cycp ?s bin input ? pulse width t bll 8 t cycp ?s ain -? bin - time t aubu 4 t cycp ?s bin -? ain time t buad 4 t cycp ?s ain ? bin time t adbd 4 t cycp ?s bin ? ain - time t bdau 4 t cycp ?s bin -? ain - time t buau 4 t cycp ?s ain -? bin time t aubd 4 t cycp ?s bin ? ain time t bdad 4 t cycp ?s ain ? bin - time t adbu 4 t cycp ?s zin input ? pulse width t zhl zin0 zin1 4 t cycp ?s zin input ? pulse width t zll 4 t cycp ?s
91 MB91103 series ain bin ain bin zin t bhl t bll t adbu t bdad t aubd t buau t ahl t all t zll t zhl t ahl t all t bdau t adbd t buad t aubu t bhl t bll
MB91103 series 92 (18) dma controller timing (v cc = +5.0 v 10%, v ss = 0.0 v, t a = ?0 c to +70 c) parameter symbol pin condition value unit remarks min. max. dreq input pulse width t drwh dreq0 dreq1 2 t cyc ?s dack ? output pulse width t dawh dack0 dack1 t cyc 3 t cyc ns dack ? output pulse width t dawl dack0 dack1 t cyc 3 t cyc ns clk dreq0, dreq1 dack0, dack1 (??output) 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v dack0, dack1 (??output) t cyc t drwh t dawh t dawl
93 MB91103 series 5. a/d conversion block electrical characteristics (av cc = v cc = +4.5 v to +5.5 v, av ss = v ss = 0.0 v, t a = ?0 c to +70 c, +4.5 v avrh ?avrl) *1: v cc = 5.0 v 10%, machine clock of 25 mhz *2: current value for a/d converters not in operation, cpu stop mode (v cc = av cc = avrh = 5.0 v) notes: as the absolute value of |avrh-avrl| decreases, relative error increases. output impedance of external circuit of analog input under following conditions; output impedance of external circuit < 7 k w approx. if output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling (sampling time is 5.6 m s for a machine clock of 25 mhz). parameter symbol pin value unit min. typ. max. resolution 10 10 bit total error 3.0 lsb linearity error 2.0 lsb differentiation linearity error 1.5 lsb zero transition voltage v ot an0 to an7 avrl ?1.5 avrl + 0.5 avrl + 2.5 lsb full-scale transition voltage v fst an0 to an7 avrh ?4.5 avrh ?1.5 avrh + 0.5 lsb conversion time 5.6 * 1 m s analog port input current i ain an0 to an7 0.1 10 m a analog input voltage v ain an0 to an7 avrl avrh v reference voltage avrh avrl av cc v avrl av ss avrh v power supply current i a av cc ?ma i ah 5 * 2 m a reference voltage supply current i r avrh 200 m a i rh 170 * 2 m a conversion variance between channels an0 to an7 4 lsb comparator analog input r on1 r on2 c 1 c 0 r on1 = 1.5 k w approx. r on2 = 0.5 k w approx. r on3 = 0.5 k w approx. r on4 = 0.5 k w approx. c 0 = 60 pf approx. c 1 = 4 pf approx. r on3 r on4 sample & hold circuit analog input circuit model plan note: listed values are for reference purposes only.
MB91103 series 94 6. de?itions of a/d converter descriptions resolution the smallest change in analog voltage detected by a/d converter. linearity error a deviation of actual conversion characteristic from a line connecting the zero-traction point (between 00 0000 0000 ? 00 0000 00001) to the full-scale transition point (between 11 1111 1110 ? 11 1111 1111). differential linearity error a deviation of a step voltage for changing the lsb of output code from ideal input voltage. total error a difference between actual value and theoretical value. the overall error includes zero-transition error, full- scale transition error and linearity error. (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh total error analog input actual conversion characteristic 1.5lsb' {1lsb' (n?)+0.5lsb'} v nt (measured value) actual conversion characteristic ideal characteristic 0.5 lsb' 1lsb' (ideal value) = (ideal value) = avrl + 0.5 lsb' [v] v ot ' (ideal value) = avrl + 1.5 lsb' [v] v fst ' [v] avrh ?avrl 1024 total error of digital output n = v nt ?{1 lsb' (n ?1) + 0.5 lsb'} 1 lsb' v nt : a voltage for causing transition of digital output from (n?) to n digital output
95 MB91103 series (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh linearity error analog input actual conversion characteristic {1 lsb (n ?1) + v ot } v nt actual conversion characteristic ideal characteristic 1 lsb = [v] v fst ?v ot 1022 linearity error of digital output n = v nt ?{1 lsb' (n ?1) + v ot } 1 lsb v ot : a voltage for causing transition of digital output from (000) h to (001) h (measured value) v fst (measured value) v ot (measured value) n? avrl avrh differential linearity error analog input n? n n+1 actual characteristic ideal characteristic actual conversion characteristic v nt (measured value) v (n+1)t (measured value) [lsb] differential linearity error of digital output n = v (n+1)t ?v nt 1 lsb [lsb] ?1 v fst : a voltage for causing transition of digital output from (3fe) h to (3ff) h digital output digital output
MB91103 series 96 n output vs load capacitance characteristic output vs load capacitance characteristic 3.5 3 2.5 2 1.5 1 0.5 0 t (ns) 80 85 90 95 100 105 110 115 120 c (pf)
97 MB91103 series n instructions 1. how to read instruction set summary (1) names of instructions. instructions marked with * are not included in cpu speci?ations. these are extended instruction codes added/extended at assembly language levels. (2) addressing modes speci?d as operands are listed in symbols. refer to ?. addressing mode symbols for further information. (3) instruction types. (4) hexa-decimal expressions of instructions. (5) number of machine cycles needed for execution. a: memory access cycle. may be extended by ready function. b: b: memory access cycle. may be extended by ready function. if an object register in a ld operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: if an immediately following instruction operates to an object of r15, ssp or usp in read/write mode or if the instruction belongs to instruction format a group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: if an immediately following instruction refers to mdh/mdl, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. for a, b, c and d, minimum execution cycle is 1. (6) change in ?g sign. flag meanings n : negative ?g z : zero ?g v : over ?g c : carry ?g flag change c : change : no change 0 : clear 1 : set (7) operation carried out by instruction. mnemonic type op ~ nzvc operation remarks add rj, ri * add #s5, ri , , a c , , a6 a4 , , 1 1 , , cccc cccc , , ri + rj ? ri ri + s5 ? ri , , (1) (2) (3) (4) (5) (6) (7)
MB91103 series 98 2. addressing mode symbols ri : register direct (r0 to r15, ac, fp, sp) rj : register direct (r0 to r15, ac, fp, sp) r13 : register direct (r13, ac) ps : register direct (program status register) rs : register direct (tbr, rp, ssp, usp, mdh, mdl) cri : register direct (cr0 to cr15) crj : register direct (cr0 to cr15) #i8 : unsigned 8-bit immediate (?28 to 255) note: ?28 to ? are interpreted as 128 to 255 #i20 : unsigned 20-bit immediate (?x80000 to 0xfffff) note: ?x7ffff to ? are interpreted as 0x7ffff to 0xfffff #i32 : unsigned 32-bit immediate (?x80000000 to 0xffffffff) note: ?x80000000 to ? are interpreted as 0x80000000 to 0xffffffff #s5 : signed 5-bit immediate (?6 to 15) #s10 : signed 10-bit immediate (?12 to 508, multiple of 4 only) #u4 : unsigned 4-bit immediate (0 to 15) #u5 : unsigned 5-bit immediate (0 to 31) #u8 : unsigned 8-bit immediate (0 to 255) #u10 : unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : unsigned 8-bit direct address (0 to 0xff) @dir9 : unsigned 9-bit direct address (0 to 0x1fe, multiple of 2 only) @dir10 : unsigned 10-bit direct address (0 to 0x3fc, multiple of 4 only) label9 : signed 9-bit branch address (?x100 to 0xfc, multiple of 2 only) label12 : signed 12-bit branch address (?x800 to 0x7fc, multiple of 2 only) label20 : signed 20-bit branch address (?x80000 to 0x7ffff) label32 : signed 32-bit branch address (?x80000000 to 0x7fffffff) @ri : register indirect (r0 to r15, ac, fp, sp) @rj : register indirect (r0 to f15, ac, fp, sp) @(r13, rj) : register relative indirect (rj: r0 to r15, ac, fp, sp) @(r14, disp10) : register relative indirect (disp10: ?x200 to 0x1fc, multiple of 4 only) @(r14, disp9) : register relative indirect (disp9: ?x100 to 0xfe, multiple of 2 only) @(r14, disp8) : register relative indirect (disp8: ?x80 to 0x7f) @(r15, udisp6) : register relative (udisp6: 0 to 60, multiple of 4 only) @ri+ : register indirect with post-increment (r0 to r15, ac, fp, sp) @r13+ : register indirect with post-increment (r13, ac) @sp+ : stack pop @?p : stack push (reglist) : register list
99 MB91103 series 3. instruction types add, addn, cmp, lsl, lsr and asr instructions only msb type a ri lsb rj op type b type c type *c type d type e type f 16 bit 4 4 8 op i8/o8 ri 484 ri u4/m4 op 4 4 8 op s5/u5 ri 754 op u8/rel8/dir/reglist 88 op sub-op ri 844 op rel11 511
MB91103 series 100 4. detailed description of instructions add/subtract operation instructions compare operation instructions logical operation instructions mnemonic type op cycle n z v c operation remarks add rj, ri * add #s5, ri add #u4, ri add2 #u4, ri a c c c a6 a4 a4 a5 1 1 1 1 cccc cccc cccc cccc ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension addc rj, ri a a7 1 cccc ri + rj + c ? ri add operation with sign addn rj, ri * addn #s5, ri addn #u4, ri addn2 #u4, ri a c c c a2 a0 a0 a1 1 1 1 1 ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension sub rj, ri a ac 1 cccc ri rj ? ri subc rj, ri a ad 1 cccc ri rj c ? ri subtract operation with carry subn rj, ri a ae 1 ri rj ? ri mnemonic type op cycle n z v c operation remarks cmp rj, ri * cmp #s5, ri cmp #u4, ri cmp2 #u4, ri a c c c aa a8 a8 a9 1 1 1 1 cccc cccc cccc cccc ri ?rj ri ?s5 ri + extu (i4) ri + extu (i4) msb is interpreted as a sign in assembly lamnguage zero-extension sign-extension mnemonic type op cycle n z v c operation remarks and rj, ri and rj, @ri andh rj, @ri andb rj, @ri a a a a 82 84 85 86 1 1+2a 1+2a 1+2a cc cc cc cc ri & = rj (ri) & = rj (ri) & = rj (ri) & = rj word word half word byte or rj, ri or rj, @ri orh rj, @ri orb rj, @ri a a a a 92 94 95 96 1 1+2a 1+2a 1+2a cc cc cc cc ri | = rj (ri) | = rj (ri) | = rj (ri) | = rj word word half word byte eor rj, ri eor rj, @ri eorh rj, @ri eorb rj, @ri a a a a 9a 9c 9d 9e 1 1+2a 1+2a 1+2a cc cc cc cc ri ^ = rj (ri) ^ = rj (ri) ^ = rj (ri) ^ = rj word word half word byte
101 MB91103 series bit manipulation instructions *1: assembler generates bandl if result of logical operation ?8&0x0f leaves an active (set) bit and generates bandh if ?8&0xf0 leaves an active bit. depending on the value in the ?8 format, both bandl and bandh may be generated. *2: assembler generates borl if result of logical operation ?8&0x0f leaves an active (set) bit and generates borh if ?8&0xf0 leaves an active bit. *3: assembler generates beorl if result of logical operation ?8&0x0f leaves an active (set) bit and generates beorh if ?8&0xf0 leaves an active bit. add/subtract operation instructions *1: divos, div1 32, div2, div3 and div4s are generated. a total instruction code length of 72 bytes. *2: divou and div1 32 are generated. a total instruction code length of 66 bytes. mnemonic type op cycle n z v c operation remarks bandl #u4, @ri bandh #u4, @ri * band #u8, @ri * 1 c c 80 81 1+2a 1+2a (ri) & = (0xf0 + u4) (ri) & = ((u4 < < 4) + 0x0f) (ri) & = u8 manipulate lower 4 bits manipulate upper 4 bits borl #u4, @ri borh #u4, @ri * bor #u8, @ri * 2 c c 90 91 1+2a 1+2a (ri) | = u4 (ri) | = (u4 < < 4) (ri) | = u8 manipulate lower 4 bits manipulate upper 4 bits beorl #u4, @ri beorh #u4, @ri * beor #u8, @ri * 3 c c 98 99 1+2a 1+2a (ri) ^ = u4 (ri) ^ = (u4 < < 4) (ri) ^ = u8 manipulate lower 4 bits manipulate upper 4 bits btstl #u4, @ri btsth #u4, @ri c c 88 89 2+a 2+a 0c cc (ri) & u4 (ri) & (u4 < < 4) test lower 4 bits test upper 4 bits mnemonic type op cycle n z v c operation remarks mul rj, ri mulu rj, ri mulh rj, ri muluh rj, ri a a a a af ab bf bb 5 5 3 3 ccc ccc cc cc ri * rj ? mdh, mdl ri * rj ? mdh, mdl ri * rj ? mdl ri * rj ? mdl 32-bit*32-bit = 64-bit unsigned 16-bit*16-bit = 32-bit unsigned divos ri divou ri div1 ri div2 ri div3 div4s * div ri * 1 * divu ri * 2 e e e e e e 97? 97? 97? 97? 9f? 9f? 1 1 d 1 1 1 36 33 ?? ?? ?? ?? mdl/ri ? mdl, mdl%ri ? mdh mdl/ri ? mdl, mdl%ri ? mdh step calculation 32-bit/32-bit = 32-bit
MB91103 series 102 shift instructions immediate value set/16-bit/32-bit immediate value transfer instruction * : if an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. if an immediate value contains relative value or external reference, assembler selects i32. memory load instructions * : assembler calculates and set the result in the ?ld of o8, o4 format given by hardware speci?ation. disp10/4 ? o8, disp9/2 ? o8, disp8 ? o8, disp10, disp9, disp8 are signed udisp6/4 ? o4, udisp6 are unsigned. mnemonic type op cycle n z v c operation remarks lsl rj, ri * lsl #u5, ri (u5: 0 ~ 31) lsl #u4, ri * lsl2 #u4, ri a c c c b6 b4 b4 b5 1 1 1 1 cc? cc? cc? cc? ri < < rj ? ri ri < < u5 ? ri ri < < u4 ? ri ri < < (u4 + 16) ? ri logical shift lsr rj, ri * lsr #u5, ri (u5: 0 ~ 31) lsr #u4, ri * lsr2 #u4, ri a c c c b2 b0 b0 b1 1 1 1 1 cc? cc? cc? cc? ri > > rj ? ri ri > > u5 ? ri ri > > u4 ? ri ri > > (u4 + 16) ? ri logical shift asr rj, ri * asr #u5, ri (u5: 0 ~ 31) asr #u4, ri * asr2 #u4, ri a c c c ba b8 b8 b9 1 1 1 1 cc? cc? cc? cc? ri > > rj ? ri ri > > u5 ? ri ri > > u4 ? ri ri > > (u4 + 16) ? ri logical shift mnemonic type op cycle n z v c operation remarks ldi:32 #i32, ri ldi:20 #i20, ri ldi:8 #i8, ri * ldi # {i8 | i20 | i32}, ri e c b 9f? 9b c0 3 2 1 i32 ? ri i20 ? ri i8 ? ri {i8 | i20 | i32} ? ri upper 12-bit is zero-extended upper 24-bit is zero-extended mnemonic type op cycle n z v c operation remarks ld @rj, ri ld @(r13, rj), ri ld @(r14, disp10), ri ld @(r15, udisp6), ri ld @r15 +, ri ld @r15 +, rs ld @r15 +, ps a a b c e e e 04 00 20 03 07? 07? 07? b b b b b b 1+a+b cccc (rj) ? ri (r13 + rj) ? ri (r14 + disp10) ? ri (r15 + udisp6) ? ri (r15) ? ri, r15 + = 4 (r15) ? rs, r15 + = 4 (r15) ? ps, r15 + = 4 rs: special register * lduh @rj, ri lduh @(r13, rj), ri lduh @(r14, disp9), ri a a b 05 01 40 b b b (rj) ? ri (r13 + rj) ? ri (r14 + disp9) ? ri zero-extension zero-extension zero-extension ldub @rj, ri ldub @(r13, rj), ri ldub @(r14, disp8), ri a a b 06 02 60 b b b (rj) ? ri (r13 + rj) ? ri (r14 + disp8) ? ri zero-extension zero-extension zero-extension
103 MB91103 series memory store instructions * : assembler calculates and set the result in the ?ld of o8, o4 format given by hardware speci?ation. disp10/4 ? o8, disp9/2 ? o8, disp8 ? o8, disp10, disp9, disp8 are signed udisp6/4 ? o4, udisp6 are unsigned. transfer instructions between registers * : special registers rs: tbr, rp usp, ssp, mdh, mdl mnemonic type op cycle n z v c operation remarks st ri, @rj st ri, @(r13, rj) st ri, @(r14, disp10) st ri, @(r15, udisp6) st ri, @?15 st rs, @?15 st ps, @?15 a a b c e e e 14 10 30 13 17? 17? 17? a a a a a a a ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp10) ri ? (r15 + usidp6) r15 ?= 4, ri ? (r15) r15 ?= 4, rs ? (r15) r15 ?= 4, ps ? (r15) word word word rs: special register * sth ri, @rj sth ri, @(r13, rj) sth ri, @(r14, disp9) a a b 15 11 50 a a a ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp9) half word half word half word stb ri, @rj stb ri, @(r13, rj) stb ri, @(r14, disp8) a a b 16 12 70 a a a ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp8) byte byte byte mnemonic type op cycle n z v c operation remarks mov rj, ri mov rs, ri mov ri, rs mov ps, ri mov ri, ps a a a e e 8b b7 b3 17? 07? 1 1 1 1 c cccc rj ? ri rs ? ri ri ? rs ps ? ri ri ? ps transfer between general-purpose registers rs: special register rs: special register *
MB91103 series 104 normal branch (non-delay) instructions notes: number of cycles ?/1 indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. assembler calculates and set the result in the ?ld of rel11 and rel8 format given by hardware speci?ation. (label12 ?pc ?2)/2 ? rel11, (label9 ?pc ?2)/2 ? rel8, label12, label9 are signed. mnemonic type op cycle n z v c operation remarks jmp @ri e 97? 2 ri ? pc call label12 call @ri f e d0 97? 2 2 pc + 2 ? rp, pc + 2 + (label12 ?pc ?2) ? pc pc + 2 ? rp, ri ? pc ret e 97? 2 rp ? pc return int #u8 inte d e 1f 9f? 3+3a 3+3a ssp ?= 4, ps ? (ssp), ssp ?= 4, pc + 2 ? (ssp), 0 ? i ?g, 0 ? s ?g, (tbr + 0x3fc ?u8 4) ? pc ssp ?= 4, ps ? (ssp), ssp ?= 4, pc + 2 ? (ssp), 0 ? s ?g, (tbr + 0x3d8) ? pc for emulator reti e 97? 2+2a cccc (r15) ? pc, r15 ?= 4, (r15) ? ps, r15 ?= 4 bra label9 bno label9 beq label9 bne label9 bc label9 bnc label9 bn label9 bp label9 bv label9 bnv label9 blt label9 bge label9 ble label9 bgt label9 bls label9 bhi label9 d d d d d d d d d d d d d d d d e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef 2 1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 pc + 2 + (label9 ? pc ?2) ? pc non-branch if (z = = 1) then pc + 2 + (label9 pc ?2) ? pc pcx/z = = 0 pcs/c = = 1 pcs/c = = 0 pcs/n = = 1 pcs/n = = 0 pcs/v = = 1 pcs/v = = 0 pcs/v xor n = = 1 pcs/v xor n = = 0 pcs/(v xor n) or z = = 1 pcs/(v xor n) or z = = 0 pcs/c or z = = 1 pcs/c or z = = 0
105 MB91103 series branch instructions with delays notes: assembler calculates and set the result in the ?ld of rel11 and rel8 format given by hardware speci?ation. (label12 ?pc ?2)/2 ? rel11, (label9 ?pc ?2)/2 ? rel8, label12, label9 are signed. delayed branch operation always executes next instruction (delay slot) before making a branch. instructions allowed to be stored in the delay slot are all 1-cycle, a, b, c and d-cycle instructions. multiple- cycle instructions are no to allowed on the delay slot. mnemonic type op cycle n z v c operation remarks jmp:d @ri e 9f? 1 ri ? pc call:d label12 call:d @ri f e d8 9f? 1 1 pc + 4 ? rp, pc + 2 + (label12 ?pc ?2) ? pc pc + 4 ? rp, ri ? pc ret:d e 9f? 1 rp ? pc return bra:d label9 bno:d label9 beq:d label9 bne:d label9 bc:d label9 bnc:d label9 bn:d label9 bp:d label9 bv:d label9 bnv:d label9 blt:d label9 bge:d label9 ble:d label9 bgt:d label9 bls:d label9 bhi:d label9 d d d d d d d d d d d d d d d d f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 pc + 2 + (label9 ? pc ?2) ? pc non-branch if (z = = 1) then pc + 2 + (label9 pc ?2) ? pc pcs/z = = 0 pcs/c = = 1 pcs/c = = 0 pcs/n = = 1 pcs/n = = 0 pcs/v = = 1 pcs/v = = 0 pcs/v xor n = = 1 pcs/v xor n = = 0 pcs/(v xor n) or z = = 1 pcs/(v xor n) or z = = 0 pcs/c or z = = 1 pcs/c or z = = 0
MB91103 series 106 others *1: for s10 format, assembler calculates s10/4 and convert to s8 format. s10 is signed. *2: if either of r0 to r7 is speci?d in reglist, assembler generates ldm0. if either of r8 to r15 is speci?d, assembler generates ldm1. both ldm0 and ldm1 may be generated. *3: if either of r0 to r7 is speci?d in reglist, assembler generates stm0. if either of r8 to r15 is speci?d, assembler generates stm1. both stm0 and stm1 may be generated. *4: for u10 format, assembler calculates u10/4 and convert to s8 format. u10 is unsigned. notes: number of cycles needed for execution of ldm0 (reglist) and ldm1 (reglist) is given by the following calculation; a*(n ?1) + b + 1 where n is number of registers speci?d. number of cycles needed for execution of stm0 (reglist) and stm1 (reglist) is given by the following calculation; a*n + 1 where n is number of registers speci?d. mnemonic type op cycle n z v c operation remarks nop e 9f? 1 no changes andccr #u8 orccr #u8 d d 83 93 c c cccc cccc ccr and u8 ? ccr ccr or u8 ? ccr stilm #u8 d 87 1 i8 ? ilm set ilm immediate value addsp #s10 * 1 d a3 1 r15 + = s10 add sp instruction extsb ri extub ri extsh ri extuh ri e e e e 97? 97? 97? 97? 1 1 1 1 sign extension 8 ? 32-bit zero extension 8 ? 32-bit sign extension 16 ? 32 bit zero extension 16 ? 32-bit ldm0 (reglist) ldm1 (reglist) * ldm (reglist) * 2 d d 8c 8d (r15) ? reglist, r15 increment (r15) ? reglist, r15 increment (r15) ? reglist, r15 increment load-multi r0 to r7 load-multi r8 to r15 load-multi r0 to r15 stm0 (reglist) stm1 (reglist) * stm2 (reglist) * 3 d d 8e 8f r15 decrement, reglist ? (r15) r15 decrement, reglist ? (r15) r15 decrement, reglist ? (r15) store-multi r0 to r7 store-multi r8 to r15 store-multi r0 to r15 enter #u10 * 4 d 0f 1+a r14 ? (r15 ?4), r15 ?4 ? r14, r15 ?u10 ? r15 entrance processing of function leave e 9f? b r14 + 4 ? r15, (r15 ?4) ? r14 exit processing of function xchb @rj, ri a 8a 2a rj ? temp (rj) ? ri temp ? (rj) for semafo management byte data
107 MB91103 series 20-bit normal branch macro instructions *1: call20 (1) if label20?c? is between ?x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label20?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call @ri *2: bra20 (1) if label20?c? is between ?x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label20?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp @ri *3: bcc20 (beq20 to bhi20) (1) if label20?c? is between ?x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label20?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp @ri false: mnemonic operation remarks * call20 label20, ri next instruction address ? rp, label20 ? pc ri: temporary register * 1 * bra20 label20, ri * beq20 label20, ri * bne20 label20, ri * bc20 label20, ri * bnc20 label20, ri * bn20 label20, ri * bp20 label20, ri * bv20 label20, ri * bnv20 label20, ri * blt20 label20, ri * bge20 label20, ri * ble20 label20, ri * bgt20 label20, ri * bls20 label20, ri * bhi20 label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
MB91103 series 108 20-bit delayed branch macro instructions *1: call20:d (1) if label20?c? is between ?x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label20?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call:d @ri *2: bra20:d (1) if label20?c? is between ?x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label20?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp:d @ri *3: bcc20:d (beq20:d to bhi20:d) (1) if label20?c? is between ?x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label20?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp:d @ri false: mnemonic operation remarks * call20:d label20, ri next instruction address + 2 ? rp, label20 ? pc ri: temporary register * 1 * bra20:d label20, ri * beq20:d label20, ri * bne20:d label20, ri * bc20:d label20, ri * bnc20:d label20, ri * bn20:d label20, ri * bp20:d label20, ri * bv20:d label20, ri * bnv20:d label20, ri * blt20:d label20, ri * bge20:d label20, ri * ble20:d label20, ri * bgt20:d label20, ri * bls20:d label20, ri * bhi20:d label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
109 MB91103 series 32-bit normal macro branch instructions *1: call32 (1) if label32?c? is between ?x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label32?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call @ri *2: bra32 (1) if label32?c? is between ?x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label32?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp @ri *3: bcc32 (beq32 to bhi32) (1) if label32?c? is between ?x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label32?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp @ri false: mnemonic operation remarks * call32 label32, ri next instruction address ? rp, label32 ? pc ri: temporary register * 1 * bra32 label32, ri * beq32 label32, ri * bne32 label32, ri * bc32 label32, ri * bnc32 label32, ri * bn32 label32, ri * bp32 label32, ri * bv32 label32, ri * bnv32 label32, ri * blt32 label32, ri * bge32 label32, ri * ble32 label32, ri * bgt32 label32, ri * bls32 label32, ri * bhi32 label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
MB91103 series 110 32-bit delayed macro branch instructions *1: call32:d (1) if label32?c? is between ?x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label32?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call:d @ri *2: bra32:d (1) if label32?c? is between ?x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label32?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp:d @ri *3: bcc32:d (beq32:d to bhi32:d) (1) if label32?c? is between ?x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label32?c? is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp:d @ri false: mnemonic operation remarks * call32:d label32, ri next instruction address + 2 ? rp, label32 ? pc ri: temporary register * 1 * bra32:d label32, ri * beq32:d label32, ri * bne32:d label32, ri * bc32:d label32, ri * bnc32:d label32, ri * bn32:d label32, ri * bp32:d label32, ri * bv32:d label32, ri * bnv32:d label32, ri * blt32:d label32, ri * bge32:d label32, ri * ble32:d label32, ri * bgt32:d label32, ri * bls32:d label32, ri * bhi32:d label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
111 MB91103 series direct addressing instructions note: assembler calculates as follows and set the result value to dir8, dir9 and dir10 ?lds. dir8 ? dir, dir9/2 ? dir, dir10/4 ? dir, dir8, dir9, dir10 are unsigned. resource instructions co-processor control instructions {cri | crj}: = cr0 | cr1 | cr2 | cr3 | cr4 | cr5 | cr6 | cr7 | cr8 | cr9 | cr10 | cr11 | cr12 | cr13 | cr14 | cr15 u4: specify channel u8: specify command note: these instructions are not valid because this model does not have a co-processor. mnemonic type op cycle n z v c operation remarks dmov @dir10, r13 dmov r13, @dir10 dmov @dir10, @r13+ dmov @r13+, @dir10 dmov @dir10, @?15 dmov @r15+, @dir10 d d d d d d 08 18 0c 1c 0b 1b b a 2a 2a 2a 2a (dir10) ? r13 r13 ? (dir10) (dir10) ? (r13), r13 + = 4 (r13) ? (dir10), r13 + = 4 r15 ?= 4, (r15) ? (dir10) (r15) ? (dir10), r15 + = 4 word word word word word word dmovh @dir9, r13 dmovh r13, @dir9 dmovh @dir9, @r13+ dmovh @r13+, @dir9 d d d d 09 19 0d 1d b a 2a 2a (dir9) ? r13 r13 ? (dir9) (dir9) ? (r13), r13 + = 2 (r13) ? (dir9), r13 + = 2 half word half word half word half word dmovb @dir8, r13 dmovb r13, @dir8 dmovb @dir8, @r13+ dmovb @r13+, @dir8 d d d d 0a 1a 0e 1e b a 2a 2a (dir8) ? r13 r13 ? (dir8) (dir8) ? (r13), r13 + + (r13) ? (dir8), r13 + + byte byte byte byte mnemonic type op cycle n z v c operation remarks ldres @ri+, #u4 stres #u4, @ri+ c c bc bd a a (ri) ? u4 resource ri + = 4 u4 resource ? (ri) ri + = 4 u4: channel number u4: channel number mnemonic type op cycle n z v c operation remarks copop #u4, #u8, crj, cri copld #u4, #u8, rj, cri copst #u4, #u8, crj, ri copsv #u4, #u8, crj, ri e e e e 9f? 9f? 9f? 9f? 2+a 1+2a 1+2a 1+2a calculation rj ? cri crj ? ri crj ? ri no error traps
MB91103 series 112 n ordering information part number package remarks MB91103 160-pin plastic qfp fpt-160p-m03
113 MB91103 series n package dimensions lead no. 1 160 121 120 81 80 41 40 (.012.004) 0.300.10 0.65(.0256)typ 0.20(.008) 0.25(.010) 0.18(.007)max 0.53(.021)max index 0.10(.004) m 0.13(.005) (.006.002) 0.150.05 ref (.998) 25.35 (1.197.016) 30.400.40 (stand off) 0(0)min 3.85(.152)max 28.000.20(1.102.008)sq 32.000.40(1.260.016)sq "b" "a" 0 10 0.800.20(.031.008) details of "b" part details of "a" part 1994 fujitsu limited f160004s-3c-2 c dimensions in mm (inches) (fpt-160p-m03) 160-pin plastic qfp
MB91103 series 114 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9704 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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